Soft error detection in a memory system

1. An integrated circuit (IC) device comprising:

a first memory device having a first set of bit cells arranged in a first plane;

a second memory device having a second set of bit cells arranged in a second plane oriented in parallel to the first plane and physically stacked with regard to the first memory device to physically overlay the first memory device with a portion of the second set of bit cells physically overlaying the first set of bit cells between external interconnects; and

one or more memory controllers configured to:

detect a first error in data stored in the first memory device at a first physical location in the IC device,

upon detecting the first error, determine whether there is a second error in data stored in the second memory device in a second physical location in the IC device near the first physical location, and translate an address of the first physical location to an address at the second physical location and determine the first physical location and the second physical location based on an origin and coordinates or dimensions of the first and second memory devices.

2. The integrated circuit device of claim 1 wherein:

the first and second memory devices have a same size.

3. The integrated circuit device of claim 1 wherein:

the first memory device has a different size than the second memory device.

4. The integrated circuit device of claim 1 wherein:

a memory controller of the one or more memory controllers is configured to test multiple physical locations in the IC device near the first physical location to determine whether there is the second error in the data in the second memory device.

5. The integrated circuit device of claim 1 wherein:

the first memory device is coupled to a first of the one or more memory controllers;

the second memory device is coupled to a second of the one or more memory controllers,

the first of the one or more memory controllers is configured to communicate the address or the location of the first error to the second of the one or more memory controller, and

the second memory controller determines whether the second error is based on the address or the location of the first error.

6. The integrated circuit device of claim 1 wherein:

the one or more memory controllers are configured to correct the first and second errors.

7. The integrated circuit device of claim 1 wherein:

the first and second memory devices are coupled to a single one of the one or more memory controllers.

8. The integrated circuit device of claim 1 wherein:

the one or more memory controllers are at the same die.

9. The integrated circuit device of claim 1 wherein:

the first memory device includes a first die and the second memory device includes a second die distinct from the first die.

10. A packaged integrated circuit device comprising:

a first memory device including first bit cells positioned on a first plane;

a second memory device including second bit cells positioned on a second plane oriented in parallel to the first plane, wherein the first and second memory devices are physically stacked with regard to each other and the second bit cells physically overlay the first bit cells between external interconnects;

one or more memory controllers configured to detect an error in data in one of the bit cells in the first memory device and, based on an address of the one of the bit cells, determine whether there is an error in data of a bit cell in a location of the second memory device near the address of the one of the bit cells in the first memory device.

11. The device of claim 10 further comprising:

a third memory device including bit cells, wherein the one or more memory controllers is configured to, based on an address of the one of the bit cells, determine whether there is an error in data of a bit cell in a location of the third memory device near the address of the one of the bit cells in the first memory device.

12. The device of claim 11 wherein the third memory device is stacked with the first and second memory devices.

13. The device of claim 12 wherein at least one of the first, second, and third memory devices has a different size than another of the first, second and third memory devices.

14. The device of claim 10 wherein the first memory device is coupled to a first of the one or more memory controllers, the second memory device is coupled to a second of the one or more memory controllers.

15. A method of detecting errors in a memory device, comprising:

detecting an error in a bit cell of a first memory device;

determining an address of the bit cell with the error;

determining a range of addresses of bit cells in a second memory device physically stacked with regard to the first memory device to physically overlay the first memory device and the bit cell of the first memory device between external interconnects, wherein the range of addresses correspond to locations near a location of the address of the bit cell with the error in the first memory device;

detecting whether there is another error in one or more of the bit cells in the range of addresses in the second memory device; and

correcting the error in the bit cell of the first memory device; and

if the other error is detected, correcting the other error in the second memory device.

16. The method of claim 15 further comprising:

determining the range of addresses based on an origin location of the first and second devices.

17. The method of claim 15 further comprising:

using a first memory controller coupled to the first and second memory devices to detect the error and the other error.

18. The method of claim 15 wherein:

using a first memory controller coupled to the first memory device to detect the error; and

using a second memory controller coupled to the second memory device to detect the other error.