Vertical channel field-effect transistor (FET) process compatible long channel transistors
Embodiments of the present invention provide methods and systems for co-integrating a short-channel vertical transistor and a long-channel transistor. One method may include: from a starting substrate, forming a wide fin, wherein the wide fin comprises a wide active region; depositing a recess mask over a top surface of the starting substrate; recessing a long channel based on the deposited recess mask; depositing a gate electrode and a gate material, to form a gate structure; and forming SD contacts in an SD region of the long-channel transistor.
1. A method for co-integrating a short-channel vertical transistor and a long-channel transistor, the method comprising:
from a starting substrate, forming a wide fin, wherein the wide fin comprises a wide active region;
depositing a recess mask over a top surface of the starting substrate;
recessing a long channel based on the deposited recess mask, wherein the long channel is recessed to align with a top surface of a bottom spacer;
depositing a gate electrode and a gate material, to form a gate structure;
forming SD contacts in an SD region of the long-channel transistor; and
depositing the bottom spacer over the top surface of the starting substrate.
2. The method of claim 1 , wherein recessing the long channel, comprises:
forming the long channel using a variable etching width and a variable etching depth.
3. The method of claim 1 , wherein recessing the long channel comprises: etching a U-shaped channel.
4. The method of claim 1 , wherein depositing a recess mask over a top surface of the starting substrate further comprises:
patterning an opening for forming the recessed long channel.
5. The method of claim 1 , further comprising:
etching the deposited gate electrode and the gate material to expose a top portion of the wide fin.
6. The method of claim 5 , further comprising:
depositing a top spacer over a top surface of the exposed top portion of the gate electrode and the gate material.
7. The method of claim 6 , further comprising:
depositing a gate electrode mask over the top surface of the wide fin.
8. The method of claim 7 , further comprising:
etching the recess mask for removal; and
recessing a top active region of the wide fin.
9. The method of claim 1 , wherein a top SD is formed on the top surface of the wide fin using an epitaxial growth process.
10. The method of claim 1 , wherein a top SD is formed on the top surface of the wide fin using an ion implantation process.