Semiconductor memory device
According to the embodiments, the semiconductor memory device includes a semiconductor substrate, a first conducting layer, a semiconductor layer, a plurality of second conducting layer, and an electric charge accumulating layer. The first conducting layer is disposed on the semiconductor substrate via an insulating layer. The semiconductor layer is disposed on the first conducting layer and extends in a first direction above the semiconductor substrate. The plurality of the second conducting layers extends in a second direction intersecting with the first direction, and is laminated along the first direction via an insulating layer, and is disposed on the first conducting layer. The electric charge accumulating layer is disposed between the semiconductor layer and the plurality of second conducting layer. The semiconductor substrate includes an n type semiconductor region facing an end portion of the semiconductor layer.
1. A semiconductor memory device, comprising:
a semiconductor substrate having a first surface;
a first conducting layer disposed on the first surface of the semiconductor substrate via a first insulating layer;
a semiconductor layer disposed on the first conducting layer via a second insulating layer, the semiconductor layer extending in a first direction intersecting with the first surface of the semiconductor substrate;
a plurality of second conducting layers extending in a second direction intersecting with the first direction, being laminated along the first direction via a plurality of insulating layers and disposed above the first conducting layer; and
an electric charge accumulating layer disposed between the semiconductor layer and the plurality of second conducting layers, wherein
the semiconductor substrate is a p type semiconductor substrate and has an n type semiconductor region at the first surface, the n type semiconductor region facing the first conducting layer via the first insulating layer, and the n type semiconductor region being electrically isolated from the semiconductor layer via the second insulating layer.
2. The semiconductor memory device according to claim 1 , wherein
a plurality of the semiconductor layers are disposed along a third direction intersecting with the first direction and the second direction, and
the semiconductor memory device further comprises a connecting portion that connects at least one pair of the semiconductor layers one another that are disposed in the third direction.
3. The semiconductor memory device according to claim 2 , wherein
the first conducting layer covers side surfaces of the connecting portion.
4. The semiconductor memory device according to claim 2 , wherein
the connecting portion is constituted of material identical to the semiconductor layer.
5. The semiconductor memory device according to claim 2 , further comprising:
a source contact that functions as a common source line of the plurality of the semiconductor layers, wherein
the source contact is connected to the connecting portion.
6. The semiconductor memory device according to claim 1 , wherein
the n type semiconductor region include at least phosphorus or arsenic.
7. The semiconductor memory device according to claim 1 , wherein
the n type semiconductor region is not connected electrically to other parts of the semiconductor memory device.
8. The semiconductor memory device according to claim 1 , further comprising:
a tunnel insulating layer disposed between the semiconductor layer and the electric charge accumulating layer.
9. The semiconductor memory device according to claim 1 , further comprising:
a block insulating layer disposed between the electric charge accumulating layer and the plurality of second conducting layers.
10. The semiconductor memory device according to claim 1 , wherein
the electric charge accumulating layer extends in the first direction, and the electric charge accumulating layer is disposed extending over the plurality of the second conducting layers.
11. The semiconductor memory device according to claim 1 , wherein
a plurality of the semiconductor layers are disposed along a third direction that intersects with the first direction and the second direction, and
the n type semiconductor region is disposed extending over the plurality of the semiconductor layers disposed along the third direction.
12. The semiconductor memory device according to claim 1 , wherein
a plurality of the semiconductor layers are disposed along the second direction, and
the n type semiconductor region is disposed extending over the plurality of the semiconductor layers disposed along the second direction.
13. The semiconductor memory device according to claim 1 , wherein
a p type semiconductor region covers side surfaces of the n type semiconductor region in the second direction and the third direction.
14. The semiconductor memory device according to claim 1 , wherein
the semiconductor layer has a lower end located in the n type semiconductor region.
15. The semiconductor memory device according to claim 1 , wherein
the end portion of the semiconductor layer is a lower end and is located in the first conducting layer.