Methods and apparatus for an image sensor with a multi-branch transistor
Various embodiments of the present technology may comprise a method and device for a multi-source/drain transistor for use in an image sensor. The device may comprise an active region, wherein the active region comprises three doped regions. Two of the three doped region may be floating diffusion active regions, wherein each floating diffusion active region is connected to a photosensitive element. The device may comprise a multi-branch channel defined by the area underlying a gate region and substantially surrounded by the doped regions. During operation the electron path may form an “L” shape within the channel.
1. A solid-state imaging device, comprising:
a first pixel and a second pixel, wherein each pixel comprises a photosensitive element; and
a reset transistor, comprising:
a first gate region comprising an outer perimeter;
a first doped region, a second doped region, and a third doped region, wherein the doped regions are adjacent to the outer perimeter of the first gate region;
wherein the first and second doped regions comprise floating diffusion active regions; and
wherein the first pixel is coupled to the first floating diffusion active region and the second pixel is coupled to the second floating diffusion active region.
2. The solid-state image device of claim 1 , wherein the reset transistor further comprises a multi-branch channel defined by an area underlying the first gate region and adjacent to the doped regions, and wherein the multi-branch channel is substantially T-shaped.
3. The solid-state imaging device of claim 1 , wherein the first floating diffusion active region is electrically connected to the second floating diffusion active regions.
4. The solid-state imaging device of claim 1 , wherein the third doped region of the reset transistor is connected to a supply voltage.
5. The solid-state imaging device of claim 1 , further comprising an amplifier comprising a second gate region, wherein the first and second floating diffusion active regions are further electrically coupled to the second gate region.
6. The solid-state imaging device of claim 1 , wherein each pixel further comprises a transfer gate, wherein the transfer gate comprises a transistor.
7. The solid-state imaging device of claim 1 , further comprising a row select gate, wherein the row select gate comprises a transistor.
8. The solid-state imaging device of claim 1 , wherein the first gate region comprises a solid layer of polysilicon.
9. The solid-state imaging device of claim 1 , wherein the first and second pixels are separated by the reset transistor.
10. A system, comprising:
an image sensor comprising:
a plurality of pixels arranged in a two-dimensional pattern, wherein each pixel comprises a photosensitive element;
a reset transistor comprising:
a first gate region comprising an outer perimeter; and
a first doped region, a second doped region, and a third doped region, wherein the doped regions are adjacent to the outer perimeter of the first gate region;
wherein the first and second doped regions comprise floating diffusion active regions; and
wherein a first pixel is coupled to the first floating diffusion active region and a second pixel is coupled to the second floating diffusion active region;
a central processing unit electrically coupled to the image sensor; and
a memory device electrically coupled to the central processing unit.
11. The system of claim 10 , wherein the first floating diffusion active region is electrically connected to the second floating diffusion active region.
12. The system of claim 11 , further comprising an amplifier, wherein the amplifier comprises a second gate region, and wherein the first and second floating diffusion active regions are further electrically coupled to the second gate region.
13. The system of claim 10 , further comprising a multi-branch channel defined by an area underlying the first gate region and adjacent to the doped regions, and wherein the multi-branch channel is substantially T-shaped.
14. The system of claim 10 , wherein the third doped region of the reset transistor is connected to a supply voltage.