IP Library Granted Patent US 9,918,172
Granted Patent B1
US 9,918,172 · App. 15/242,358 · Granted Mar 13, 2018

Active output driver supply compensation for noise reduction

Inventors: Ivo Leonardus Coenen (Coffrane, CH); Alexander Heubi (La Chaux-de-Fonds, CH)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H04R29/00H04R25/43H04R2201/028H04R2460/01
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Quick Facts
Patent No.
US 9,918,172
App. No.
15/242,358
Granted
Mar 13, 2018
Kind
B1
Abstract

An electronic system, in some embodiments, comprises: a power source; a load coupled to the power source; an analog-to-digital converter, coupled to the power source and the load, that samples a fluctuating voltage supplied by the power source and generates a digital representation of said fluctuating voltage; control logic, coupled to the analog-to-digital converter, that generates an amplitude correction signal based on said digital representation of the fluctuating voltage and on a target voltage; correction logic, coupled to the control logic, that uses the amplitude correction signal and an audio signal to generate a switch control signal; and an output driver, coupled to the correction logic, that controls coupling between the power source and the load based on the switch control signal.

Claims (40)

1. An electronic system, comprising:

a power source;

a load coupled to the power source;

an analog-to-digital converter, coupled to the power source and the load, that samples a fluctuating voltage supplied by the power source and generates a digital representation of said fluctuating voltage;

control logic, coupled to the analog-to-digital converter, that generates an amplitude correction signal based on said digital representation of the fluctuating voltage and on a target voltage;

correction logic, coupled to the control logic, that uses the amplitude correction signal and an audio signal to generate a switch control signal; and

an output driver, coupled to the correction logic, that controls coupling between the power source and the load based on the switch control signal.

2. The system of claim 1 , wherein said output driver comprises a Class-D amplifier.

3. The system of claim 1 , further comprising a variable current load that causes said fluctuating voltage to fluctuate.

4. The system of claim 1 , wherein the correction logic comprises a sigma-delta modulator.

5. The system of claim 1 , wherein the output driver comprises an H-Bridge circuit.

6. The system of claim 1 , wherein the switch control signal is a digital 1-bit bit stream.

7. The system of claim 1 , further comprising a voltage regulator, coupled between the power source and the load, to provide the load with a regulated voltage that is less than voltages between which the fluctuating voltage fluctuates.

8. The system of claim 7 , wherein the voltage regulator is disabled when a variable current load in the system is disabled, and wherein the voltage regulator is enabled when said variable current load is enabled.

9. The system of claim 1 , wherein the control logic generates the amplitude correction signal based at least in part on an extrapolation of multiple digitized samples of the fluctuating voltage.

10. The system of claim 1 , wherein the control logic generates the amplitude correction signal at least in part by determining or approximating a ratio of said digital representation and a nominal voltage from the power source.

11. An electronic system, comprising:

a variable current load;

a power source, coupled to the variable current load, that provides a fluctuating voltage due at least in part to the variable current load;

a second load;

one or more switches to control coupling between the power source and the second load;

a sampling system, coupled to the second load, to sample a voltage provided to the second load; and

a comparator, coupled to the sampling system, that uses the sampled voltage and a reference voltage to generate a switch control signal that controls the one or more switches.

12. The system of claim 11 , wherein the one or more switches comprise n-type metal oxide semiconductor field effect transistor (n-MOSFET) switches.

13. The system of claim 11 , wherein the sampling system comprises a sample and hold switch and at least one capacitor.

14. The system of claim 11 , wherein the sampling system samples the voltage provided to the second load comprises positive and negative signal levels as referenced to 0 volts and wherein the sampling system only samples the positive signals.

15. The system of claim 11 , wherein the second load is an audio speaker.

16. The system of claim 11 , wherein the electronic system is a hearing aid device that is at least partially inserted into a human ear.

17. The system of claim 11 , wherein the power source is a portable source such as a battery.

18. The system according to claim 11 , further comprising a voltage regulator, coupled in between the power source and the output driver, to provide the second load with a regulated voltage that is less than voltages between which the fluctuating voltage fluctuates.

19. An audio noise reduction method, comprising:

taking a first measurement of a power source voltage at a first time;

taking a second measurement of said power source voltage at a second time;

calculating a rate of change based on said first and second voltage measurements;

predicting a future power source voltage based on said rate of change;

generating an amplitude correction signal based on the future power source voltage and a target load voltage;

generating a switch control signal using the amplitude correction signal and an audio signal; and

controlling one or more switches using the switch control signal to regulate the provision of power to a load.

20. The method of claim 19 , further comprising using one or more decoupling capacitors in tandem with said power source.

21. The method of claim 19 , further comprising using a voltage regulator to maintain said power provided to the load at a level that is less than the voltage range within which the power source voltage fluctuates.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 041187, FRAME 0295 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064151/0203 →
SECURITY INTEREST Recorded Dec 23, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 041187/0295 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2016
From: COENEN, IVO LEONARDUS; HEUBI, ALEXANDER
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 039491/0205 →