IP Library Granted Patent US 9,711,515
Granted Patent B1
US 9,711,515 · App. 15/246,768 · Granted Jul 18, 2017

Method of manufacturing semiconductor memory device

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Quick Facts
Patent No.
US 9,711,515
App. No.
15/246,768
Granted
Jul 18, 2017
Kind
B1
Abstract

A method of manufacturing a semiconductor memory device according to an embodiment comprises: alternately stacking first inter-layer insulating layers and first layers above a substrate; forming a first opening penetrating the layers stacked above the substrate; and forming a gate insulating layer and a semiconductor layer in the first opening. In addition, the method comprises: forming a second opening penetrating the layers stacked above the substrate; and forming a second inter-layer insulating layer on an inner wall of the second opening. Moreover, the method comprises: forming a first silicide layer and a barrier metal layer on the bottom surface of the second opening; and forming a silicon layer in the second opening such that a crevice is formed in an upper surface of the silicon layer along the second opening. Furthermore, the method comprises: removing part of the silicon layer; and siliciding the silicon layer via the crevice.

Claims (48)

1. A method of manufacturing a semiconductor memory device, comprising:

alternately stacking a plurality of first inter-layer insulating layers and first layers above a substrate;

forming a first opening that penetrates a plurality of the first inter-layer insulating layers and first layers;

forming a gate insulating layer and a semiconductor layer on an inner wall of the first opening;

forming a second opening that penetrates a plurality of the first inter-layer insulating layers and first layers;

forming a second inter-layer insulating layer on a bottom surface and an inner wall of the second opening;

removing a portion covering the bottom surface of the second opening, of the second inter-layer insulating layer;

forming a first silicide layer on the bottom surface of the second opening;

forming a barrier metal layer on an upper surface of the first silicide layer and on a side surface of the second inter-layer insulating layer;

forming a silicon layer on an upper surface and side surface of the barrier metal layer such that a crevice is formed in an upper surface of the silicon layer along the second opening;

removing part of the silicon layer; and

siliciding the silicon layer via the crevice to form a second silicide layer.

2. The method of manufacturing a semiconductor memory device according to claim 1 , further comprising the following which are performed after forming the second opening and before forming the second inter-layer insulating layer, namely:

removing the plurality of first layers via the second opening; and

forming a plurality of first conductive layers covering an upper surface and lower surface of the first inter-layer insulating layer.

3. The method of manufacturing a semiconductor memory device according to claim 1 , wherein

the first layers are conductive layers, and

a plurality of first conductive layers is formed by forming the second opening.

4. The method of manufacturing a semiconductor memory device according to claim 1 , further comprising the following which are performed after removing part of the silicon layer, namely:

forming a metal layer in the crevice;

performing heat treatment to form the second silicide layer; and

removing the metal layer.

5. The method of manufacturing a semiconductor memory device according to claim 1 , further comprising the following which is performed after forming the second silicide layer, namely

sequentially forming a second barrier metal layer and a second conductive layer on an upper surface of the second silicide layer and on the side surface of the second inter-layer insulating layer.

6. A method of manufacturing a semiconductor memory device, comprising:

alternately stacking a plurality of first inter-layer insulating layers and first layers above a substrate;

forming a first opening that penetrates a plurality of the first inter-layer insulating layers and first layers;

forming a gate insulating layer and a semiconductor layer on an inner wall of the first opening;

forming a second opening that penetrates a plurality of the first inter-layer insulating layers and first layers;

forming a second inter-layer insulating layer on a bottom surface and an inner wall of the second opening;

removing a portion covering the bottom surface of the second opening, of the second inter-layer insulating layer;

forming a first silicide layer on the bottom surface of the second opening;

forming a barrier metal layer on an upper surface of the first silicide layer and on a side surface of the second inter-layer insulating layer;

forming a silicon layer on an upper surface and side surface of the barrier metal layer to form a cavity covered by the silicon layer inside the second opening;

removing part of the silicon layer to form a third opening communicating with the cavity; and

siliciding the silicon layer via the third opening to form a second silicide layer.

7. The method of manufacturing a semiconductor memory device according to claim 6 , further comprising the following which are performed after forming the second opening and before forming the second inter-layer insulating layer, namely:

removing the plurality of first layers via the second opening; and

forming a plurality of first conductive layers covering an upper surface and lower surface of the first inter-layer insulating layer.

8. The method of manufacturing a semiconductor memory device according to claim 6 , wherein

the first layers are conductive layers, and

a plurality of first conductive layers is formed by forming the second opening.

9. The method of manufacturing a semiconductor memory device according to claim 6 , further comprising the following which are performed after forming the third opening in the silicon layer, namely:

forming a metal layer inside the third opening and the cavity;

performing heat treatment to form the second silicide layer; and

removing the metal layer.

10. The method of manufacturing a semiconductor memory device according to claim 6 , further comprising the following which is performed after forming the second silicide layer, namely

sequentially forming a second barrier metal layer and a second conductive layer on an upper surface of the second silicide layer and on the side surface of the second inter-layer insulating layer.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043541/0381 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2016
From: SONEHARA, TAKESHI; KITO, MASARU
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 039538/0924 →