Vertical field effect transistor including integrated antifuse

1. A vertical field effect transistor (FET), comprising:

a vertical semiconductor channel including a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region;

an electrically conductive gate that encapsulates the vertical semiconductor channel; and

a split-channel antifuse device between the source/drain region and the electrically conductive gate, the split-channel antifuse device including a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate, wherein the gate dielectric comprises,

a first dielectric layer that has a first thickness and has a first end that contacts the substrate; and

a second dielectric layer that has a second thickness different from the first thickness, and that has a first end contacting a second end of the first dielectric layer,

wherein the substrate is a semiconductor-on-insulator (SOI) substrate including a buried insulator layer interposed between a bulk semiconductor layer and the vertical semiconductor channel, and wherein the first dielectric layer contacts the buried insulator layer, and

wherein the first thickness is less than the second thickness such that the first dielectric layer has a first dielectric breakdown strength that is less than a second dielectric breakdown strength of the second dielectric layer.

2. The vertical FET of claim 1 , wherein the first thickness defines the first dielectric breakdown strength and the second thickness defines the second dielectric breakdown strength.

3. The vertical FET of claim 1 , wherein the vertical semiconductor channel comprises silicon (Si), the electrically conductive gate comprises a metal material, and the gate dielectric comprises an electrically insulative material.

4. A semiconductor memory cell, comprising:

a substrate extending along a first direction to define a length and second direction opposite the first direction to define a width;

a vertical semiconductor channel extending between first and second opposing ends along a third direction opposite the first and second directions, the first end on an upper surface of the substrate and the second end contacting a source/drain region; and

an electrically conductive gate encapsulating the vertical semiconductor channel,

wherein the vertical semiconductor channel has a split-channel gate dielectric interposed between the vertical semiconductor channel and the electrically conductive gate, the split-channel gate dielectric including a first dielectric layer having a first thickness and a second dielectric having a second thickness different from the first thickness, the first thickness of the first dielectric layer being less than the second thickness of the second dielectric layer,

wherein the substrate is a semiconductor-on-insulator (SOI) substrate including a buried insulator layer interposed between a bulk semiconductor layer and the vertical semiconductor channel, and wherein the first dielectric layer contacts the buried insulator layer.

5. The semiconductor memory of claim 4 , wherein the first dielectric layer includes a first end that contacts the upper surface of the substrate and a second end that directly contacts second dielectric layer, and the second dielectric layer includes a distal end that is opposite the second end of the first dielectric layer and that contacts the source/drain region.

6. The semiconductor memory cell of claim 4 , wherein the vertical semiconductor channel comprises silicon (Si), the electrically conductive gate comprises a metal material, and the split-channel gate dielectric comprises an electrically insulative material.

7. The semiconductor memory cell of claim 4 , wherein the source/drain region is configured as a bit line and the electrically conductive gate is configured as a word line.