Apparatus and method for fast conversion, compact, ultra low power, wide supply range auxiliary digital to analog converters

1. A data converter, comprising:

a single-end capacitive digital to analog converter (DAC);

a transconductance (GM) buffer having an output, a positive input coupled to the DAC and a negative input coupled to the output, wherein the buffer includes both PMOS input pair and NMOS input pair to cover an input range from ground to supply; and

a resistor and a capacitor in parallel coupled to the output at one terminal and to ground at the other terminal.

2. The data converter of claim 1 , wherein the GM buffer comprises an NMOS input pair, a PMOS input pair or both NMOS and PMOS pairs.

3. The data converter of claim 1 , wherein the GM buffer comprises a PMOS input pair, further comprising a differential input nodes INP and INN, a direct current bias current generator, and a current mirror pair with a predetermined current ratio.

4. The data converter of claim 1 , wherein when the capacitive DAC output increases from an input code, node INP voltage is increased and injects an extra current in a current mirror pair into the resistive and capacitive loads and increases an output voltage to follow an input voltage at node INP.

5. The data converter of claim 1 , wherein the GM buffer has no high-impedance node.

6. A method for performing digital to analog conversion, comprising:

providing a single-end capacitive digital to analog converter (DAC);

buffering the output of the capacitive DAC with a transconductance (GM) buffer;

providing both PMOS input pair and NMOS input pair in the GM buffer to cover an input range from ground to supply; and

driving a load comprising a resistor coupled to the output at one terminal and to ground at the other terminal and a capacitor coupled to the output at one terminal and to ground at the other terminal.

7. The method of claim 6 , wherein the GM buffer comprises an NMOS input pair, a PMOS input pair or both NMOS and PMOS input pairs.

8. The method of claim 6 , wherein the GM buffer comprises a PMOS input pair, further comprising a differential input nodes INP and INN, a direct current bias current generator, and a current mirror pair with a predetermined current ratio.

9. The method of claim 6 , wherein when the capacitive DAC output increases from an input code, node INP voltage is increased and injects an extra current in a current mirror pair into the resistive and capacitive loads and increases an output voltage to follow an input voltage at node INP.

10. The method of claim 6 , wherein the GM buffer has no high-impedance node.

11. A data converter, comprising:

a single-end capacitive digital to analog converter (DAC);

a transconductance (GM) buffer having an output, a positive input coupled to the DAC and a negative input coupled to the output; and

a resistor and a capacitor in parallel coupled to the output at one terminal and to ground at the other terminal, wherein the GM buffer comprises a PMOS input pair, further comprising a differential input nodes INP and INN, a direct current bias current generator, and a current mirror pair with a predetermined current ratio.

12. The data converter of claim 11 , wherein the GM buffer comprises an NMOS input pair, a PMOS input pair or both NMOS and PMOS pairs.

13. The data converter of claim 11 , wherein the GM buffer comprises a PMOS input pair, further comprising a differential input nodes INP and INN, a direct current bias current generator, and a current mirror pair with a predetermined current ratio.

14. The data converter of claim 11 , wherein when the capacitive DAC output increases from an input code, node INP voltage is increased and injects an extra current in a current mirror pair into the resistive and capacitive loads and increases an output voltage to follow an input voltage at node INP.