Patent Assignment
Reel/Frame 073799/0516
Assignment of Assignor's Interest
Recorded: 2025-11-30
Pages: 6
Assignor
IPGREAT INCORPORATED
Executed: 2025-11-30
Assignee
IPSMART INC.
R401 4F 130 SIWEI ROAD, NORTH DISTRICT, HSINCHU CITY, 300, TAIWAN
Covered Properties
(20)
Appapatus and Method for Fast Conversion, Compact, Ultra Low Power, Wide Supply Range Auxiliary Digital to Analog Converters
Patent:
9,621,180 →
Application:
15/247,651 →
Apparatus and Method of Self-Healing Data Converters
Patent:
9,667,263 →
Application:
15/287,560 →
Appapatus and Method for Fast Conversion, Compact, Ultra Low Power, Wide Supply Range Auxiliary Digital to Analog Converters
Patent:
9,866,236 →
Application:
15/414,516 →
Programmable Duty-Cycle Low Jitter Differential Clock Buffer
Patent:
9,979,382 →
Application:
15/451,113 →
Apparatus and Method of Self-Healing Data Converters
Patent:
9,813,075 →
Application:
15/494,532 →
System and Method of Minimizing Differential Non-Linearity (Dnl) for High Resolution Current Steering Dac
Patent:
9,843,336 →
Application:
15/494,533 →
High Speed Sar Adc Using Comparator Output Triggered Binary-Search Timing Scheme and Bit-Dependent Dac Settling
Patent:
9,774,337 →
Application:
15/594,260 →
High Speed Sar Adc Using Comparator Output Triggered Binary-Search Timing Scheme and Bit-Dependent Dac Settling
System and Method for Anti Reverse Engineering for Analog Integrated Circuit
System and Method of Minimizing Differential Non-Linearity (Dnl) for High Resolution Current Steering Dac
Patent:
10,014,874 →
Application:
15/792,563 →
Generating Enhanced Digital Images by Selectively Transforming Raster Images to Vector Drawing Segments
Sar Adc Using Value Shifted Capacitive Dac for Improved Reference Settling and Higher Conversion Rate
Process, Voltage and Temperature Optimized Asynchronous Sar Adc
Patent:
10,505,559 →
Application:
16/200,655 →
Method of Capacitive Dac Calibration for Sar Adc
Patent:
10,523,228 →
Application:
16/224,344 →
Method of Capacitive Dac Calibration for Sar Adc
Process, Voltage and Temperature Optimized Asynchronous Sar Adc
On-Chip Pattern Generator for High Speed Digital-to-Analog Converter
Patent:
10,873,339 →
Application:
16/726,788 →
Digital Corrected Two-Step Sar Adc
Patent:
10,938,399 →
Application:
16/893,946 →
Method of Data Conversion for Computing-In-Memory
Apparatus and Method of Enhancing Linearity and Expanding Output Amplitude for Current-Steering Digital-to-Analog Converters (Dac)
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
May 12, 2017
From: CHAO, YUAN-JU; CHU, TA-SHUN
To: IPGREAT INCORPORATED
Reel/Frame 042353/0472 →
Assignment of Assignor's Interest
Jun 1, 2018
From: PETERSON, JOHN
To: ADOBE SYSTEMS INCORPORATED
Reel/Frame 045965/0705 →
Change of Name
Nov 30, 2018
From: ADOBE SYSTEMS INCORPORATED
To: ADOBE INC.
Reel/Frame 047688/0635 →