System and method of minimizing differential non-linearity (DNL) for high resolution current steering DAC

1. A current steering converter fabricated using a predetermined integrated circuit technology, comprising:

a unary portion having one or more current sources;

a binary portion including:

a plurality of switches controlled by a decoder, the switches coupled to a converter output; and

a plurality of devices commonly connected at a first end and coupled to each respective switch at a second end, wherein each device size comprises (W/L)*M, where W/L is a width and length and M is an integer representing multiple number; and

a reference source coupled to the devices, wherein the current from the reference source is split equally using a current divider.

2. The converter of claim 1 , wherein the devices comprise NMOS current sources or PMOS current sources.

3. The converter of claim 1 , wherein the dimensions of the device reaches a minimum size of the technology.

4. The converter of claim 1 , wherein the least-significant-bit (LSB) comprises two devices coupled in series, each having a dimension of (W min /L)*M, and the most significant-bit (MSB) uses the dimension of a reference current source, and each bit in between uses half of the multiple number to cut the current by half, and where W min is the minimum width allowed in the technology design rule.

5. The converter of claim 1 , comprising an LSB bit 0 , bit 1 and bit 2 , wherein bit 1 has the same device size as bit 2 and splits the current by two with two switches connecting to a bit 1 device with one switch is connected to the converter output, wherein bit 0 has the same device size as bit 2 and splits the current by four with four switches connecting to a bit 0 device with one switch is connected to the converter outputs.

6. The converter of claim 5 , wherein the resistance of a resistor not connected to the converter output is trimmed to compensate for device fabrication mismatch.

7. The converter of claim 6 , wherein the adjustable load element consists of a fixed value passive resistor and an active PMOS or NMOS transistor with controlled gate voltage.

8. A method for fabricating a current steering converter with a predetermined integrated circuit technology, comprising:

forming a unary portion having one or more current sources;

forming a binary portion including a plurality of switches controlled by a decoder, the switches coupled to a converter output; and

specifying a layout for a plurality of devices commonly connected at a first end and coupled to each respective switch at a second end, wherein each device size comprises (W/L)*M, where W/L is a width and length of the device and M is an integer representing multiple number; and

generating a current from a reference source coupled to the devices, wherein the current from the reference source is split equally using a divider for the device dimension to reach a minimize size of the technology.

9. The method of claim 8 , comprising forming an LSB bit 0 , bit 1 and bit 2 , wherein bit 1 has the same device size as bit 2 and splits the current by two with two switches connecting to a bit 1 device with one switch is connected to the converter output, wherein bit 0 has the same device size as bit 2 and splits the current by four with four switches connecting to a bit 0 device with one switch is connected to the converter output.

10. The method of claim 9 , wherein the resistance of the resistor not connected to the converter output is trimmed to compensate for device fabrication mismatch.