Appapatus and method for fast conversion, compact, ultra low power, wide supply range auxiliary digital to analog converters
A data converter includes a single-end capacitive digital to analog converter (DAC); a transconductance (GM) buffer having an output, a positive input coupled to the DAC and a negative input coupled to the output; a resistor and a capacitor load in parallel coupled to the output at one terminal and to ground at the other terminal. The developed architecture of comprising single end capacitive DAC and GM-based buffer provides fast conversion rate, low current consumption, small silicon area and wide supply range for general-purpose auxiliary DAC applications.
1. A data converter, comprising:
a single-end capacitive digital to analog converter (DAC);
a transconductance (GM) buffer having an output, a positive input coupled to the DAC and a negative input coupled to the output and an input range from ground to supply;
a resistor and a capacitor in parallel coupled to the output at one terminal and to ground at the other terminal.
2. The data converter of claim 1 , wherein the GM buffer comprises an NMOS input pair, a PMOS input pair or both NMOS and PMOS pairs.
3. The data converter of claim 1 , wherein the GM buffer comprises a PMOS input pair, further comprising a differential input nodes INP and INN, a direct current bias current generator, and a current mirror pair with a predetermined current ratio.
4. The data converter of claim 1 , wherein when the capacitive DAC output increases from an input code, node INP voltage is increased and injects an extra current in a current mirror pair into the resistive and capacitive loads and increases an output voltage to follow an input voltage at node INP.
5. The data converter of claim 1 , wherein the GM buffer has no high-impedance node.
6. The data converter of claim 1 , wherein the buffer has PMOS input pair and NMOS input pair to cover an input range from ground to supply.
7. A method for performing digital to analog conversion, comprising:
providing a single-end capacitive digital to analog converter (DAC);
buffering the output of the capacitive DAC with a transconductance (GM) buffer;
using the GM buffer to cover an input range from ground to supply; and
driving a load comprising a resistor coupled to the output at one terminal and to ground at the other terminal and a capacitor coupled to the output at one terminal and to ground at the other terminal.
8. The method of claim 7 , wherein the GM buffer comprises an NMOS input pair, a PMOS input pair or both NMOS and PMOS input pairs.
9. The method of claim 7 , wherein the GM buffer comprises a PMOS input pair, further comprising a differential input nodes INP and INN, a direct current bias current generator, and a current mirror pair with a predetermined current ratio.
10. The method of claim 7 , wherein when the capacitive DAC output increases from an input code, node INP voltage is increased and injects an extra current in a current mirror pair into the resistive and capacitive loads and increases an output voltage to follow an input voltage at node INP.
11. The method of claim 7 , wherein the GM buffer has no high-impedance node.
12. The method of claim 7 , comprising providing both PMOS input pair and NMOS input pair in the buffer to cover an input range from ground to supply.
13. A data converter, comprising:
a single-end capacitive digital to analog converter (DAC);
a transconductance (GM) buffer having an output, a positive input coupled to the DAC and a negative input coupled to the output; and
a resistor and a capacitor in parallel coupled to the output at one terminal and to ground at the other terminal, and a differential input nodes, a direct current bias current generator, and a current mirror pair with a predetermined current ratio.
14. The data converter of claim 13 , wherein the GM buffer comprises an NMOS input pair, a PMOS input pair or both NMOS and PMOS pairs.
15. The data converter of claim 13 , wherein the GM buffer comprises a PMOS input pair, further comprising a differential input nodes INP and INN, a direct current bias current generator, and a current mirror pair with a predetermined current ratio.
16. The data converter of claim 13 , wherein when the capacitive DAC output increases from an input code, node INP voltage is increased and injects an extra current in a current mirror pair into the resistive and capacitive loads and increases an output voltage to follow an input voltage at node INP.