Digital corrected two-step SAR ADC
A new SARADC has two low resolution SAR (Successive Approximation Register) ADCs coupled together by an amplifier to increase the overall resolution and enhance ADC conversion rate. The gain reduction of amplifier is corrected by shifting the digital binary output position. Two SAR ADC outputs are timing aligned and summed to produce final high-resolution high conversion rate ADC output.
1. A digital corrected two-step Successive Approximation Register ADC (SARADC), comprising:
a M-bit SARADC1; and
an amplifier; and
a N-bit SARADC2; and
a digit combiner wherein the residue voltage of SARADC1 is amplified and coupled to SARADC2, wherein SARADC1 and SARADC2 outputs are aligned and summed by the digit combiner to produce a final (M+N−R) bit ADC output, and R is amplifier gain dependent reduced bit number operating the SARADC with an input/output transfer function as:
V
in
=
out
1
*
LSB
1
+
out
2
⋆
LSB
2
4
+
q
4
where Vres is a residue of a first conversion, q is a quantization error of a second conversion, LSB1 is the least significant bit (LSB) of the first conversion, and LSB2 is LSB of the second conversion.
2. The SARADC of claim 1 , comprising a capacitor inserted into M-bit capacitive DAC and asserted after binary search bit-test to subtract 0.5LSB voltage from residue voltage range of 0˜1LSB.
3. The SARADC of claim 1 , wherein the residue voltage range is shifted from 0˜1LSB to −0.5LSB to +0.5LSB to double amplifier output range and increase ADC SNR (Signal-to-Noise Ratio).
4. The SARADC of claim 1 , wherein the amplifier gain is reduced by half to avoid saturating the input range of SARADC2; SARADC2 output is digitally corrected by shifting 1 bit position to compensate the gain reduction.
5. The SARADC of claim 1 , wherein the amplifier gain is reduced by four times to reduce amplifier power consumption; SARADC2 output is digitally corrected by shifting 2 bits position to compensate a gain reduction.
6. The SARADC of claim 1 , wherein two low-resolution SARADCs are coupled by an amplifier, two low-resolution SARADC outputs are concatenated to yield a final ADC output.
7. The SARADC of claim 1 , wherein two low-resolution SARADC binary search process are executed concurrently to enhance a final ADC conversion rate.
8. The SARADC of claim 1 , wherein the SARADC1 and SARADC2 comprises the same circuitry and employ the same reference voltage to minimize design complexity and reduce the development time.
9. The SARADC of claim 1 , wherein (M+N) bit SARADC is split into M-bit SARADC and N-bit SARADC coupled by an amplifier to reduce total capacitor value from 2 (M+N) C to sum of 2 M C and 2 N C.
10. The SARADC of claim 1 , wherein the (M+N) bit SARADC is split into M-bit SARADC and N-bit SARADC coupled by an amplifier to reduce capacitor value, power consumption and area.
11. A method of enhancing Analog-to-Digital conversion rate, comprising: coupling two low resolution SARADCs with an amplifier; and executing two SARADCs concurrently to boost the final ADC conversion rate and operating the SARADC with an input/output transfer function as:
V
in
=
out
1
*
LSB
1
+
out
2
⋆
LSB
2
4
+
q
4
where Vres is a residue of a first conversion, q is a quantization error of a second conversion, LSB1 is the least significant bit (LSB) of the first conversion, and LSB2 is LSB of the second conversion.
12. A method of increasing Analog-to-Digital resolution, comprising: coupling two low resolution SARADCs with an amplifier; and concatenating two low resolution SARADC outputs to yield a final ADC output, and operating the SARADC with an input/output transfer function as:
V
in
=
out
1
*
LSB
1
+
out
2
⋆
LSB
2
4
+
q
4
where Vres is a residue of a first conversion, q is a quantization error of a second conversion, LSB1 is the least significant bit (LSB) of the first conversion, and LSB2 is LSB of the second conversion.
13. The method of claim 12 , comprising inserting a capacitor in (original) The SARADC capacitive DAC and activated after binary search process to shift the residue voltage from 0˜1LSB to +/−0.5LSB.
14. The method of claim 12 , wherein SARADC residue voltage is shifted from 0˜1LSB to +/−0.5LSB to double amplifier output range and enhance ADC SNR (Signal-to-Noise Ratio).
15. The method of claim 12 , comprising reducing the amplifier gain by half to avoid saturating the input range of second SARADC; and shifting SARADC digital outputs by 1-bit position to compensate the gain reduction and operating the SARADC with an input/output transfer function as:
V
in
=
out
1
*
LSB
1
+
out
2
⋆
LSB
2
4
+
q
4
where Vres is a residue of a first conversion, q is a quantization error of a second conversion, LSB1 is the least significant bit (LSB) of the first conversion, and LSB2 is LSB of the second conversion.
16. The method of claim 12 , comprising reducing the amplifier gain by 4 times to reduce amplifier power consumption; and shifting SARADC digital outputs by 2-bit position to compensate the gain reduction.
17. The method of claim 12 , comprising reducing the amplifier gain and digitally correcting the gain reduction by shifting digital output bit position to maintain overall SNR (Signal-to-Noise Ratio).
18. The method of claim 12 , comprising utilizing (original) The SARADC circuitry and reference voltage to minimize design complexity and reduce development time.
19. The method of claim 12 , wherein a high resolution SARADC is separated into two low resolution SARADCs coupled by an amplifier to reduce the total capacitor value.
20. The method of claim 12 , wherein a high resolution SARADC is split into two low resolution SARADCs coupled by an amplifier to reduce the power consumption and silicon area.