Hybrid hall effect magnetoelectronic gate
View Patent ↗Hybrid Hall Effect Devices implemented with Spin Transfer Torque write capability are configured as magnetoelectronic (ME) devices. These devices are useable as circuit building blocks in reconfigurable processing systems, including as logic circuits, non-volatile switches and memory cells.
1. A hybrid Hall Effect magnetoelectronic device which is configurable into different device states comprising:
a Hall cross element;
a first ferromagnetic film situated on said Hall Cross element and having a configurable magnetization orientation representing a device state;
a second ferromagnetic film having a pinned magnetization orientation;
a barrier film situated between said first ferromagnetic film and second ferromagnetic film and configured to conduct and impart a spin-torque transfer current to set the device state for said configurable magnetization orientation in io said first ferromagnetic film.
2. The device of claim 1 further including a ground coupled to said first ferromagnetic film.
3. The device of claim 1 wherein said first ferromagnetic film magnetization orientation has at least two bistable states.
4. The device of claim 1 wherein said barrier layer is comprised of aluminum oxide or magnesium oxide.
5. The device of claim 4 wherein the device performs both AND/OR functions when said first ferromagnetic film has a first initial state, and the device performs both NAND/NOR function when said first ferromagnetic film has a second initial state.
6. The device of claim 1 further including a first data input, a second data input, and a configuration input coupled to a summing node and said second ferromagnetic film.
7. The device of claim 1 wherein the device state can be read by detecting an electrical signal across said Hall cross element that is related to a fringe field imparted by said first ferromagnetic film acting on an electrical current flowing in said Hall cross element.
8. The device of claim 1 further including a CMOS inverter coupled to an output of the device.
9. The device of claim 1 further including a CMOS amplifier coupled to an output of the device.
10. The device of claim 1 wherein the device has a logical low output value of approximately 0 volts.
11. The device of claim 1 wherein the device is configured and integrated with semiconductor components in a first region of an integrated circuit as part of a non-volatile switch.
12. The device of claim 1 wherein the device is configured and integrated with semiconductor components in a first region of an integrated circuit as part of a non-volatile memory cell.
13. The device of claim 12 wherein the device is self-contained and not part of a non-volatile memory cell array.
14. The device of claim 1 wherein the device is configured and integrated with semiconductor components in a first region of an integrated circuit as part of a logic circuit.
15. The device of claim 14 wherein each logic gate in said logic circuit includes an integrated non-volatile memory cell.
16. The circuit of claim 14 wherein the logic circuit is a half-adder circuit and said device stores a result of a carry or sum operation.
17. An integrated magnetoelectronic and semiconductor circuit situated on a common integrated circuit substrate comprising:
a magnetoelectronic device situated in a first portion of the integrated circuit substrate and including:
a Hall cross element;
a first ferromagnetic film situated on said Hall Cross element and having a configurable magnetization orientation representing a device state;
a second ferromagnetic film having a pinned magnetization orientation orientation;
io a barrier film situated between said first ferromagnetic film and second ferromagnetic film and configured to conduct and impart a spin-torque transfer current to set a device state for said configurable magnetization orientation in said first ferromagnetic film;
an output for reading the device state for the magnetoelectronic device;
a semiconductor device with an input connected to said output and also situated in a first portion of the integrated circuit substrate;
wherein the integrated magnetoelectronic and semiconductor circuit are configured as one of a non-volatile switch, memory element, and logic gate.