Semiconductor memory device and method of manufacturing the same

1. A semiconductor memory device comprising:

a stacked body, the stacked body including a plurality of control gate electrodes stacked above a substrate;

a memory columnar body that extends in a first direction above the substrate and configures a memory string along with the stacked body; and

a source contact extending in the first direction and being electrically connected to one end of the memory string,

the source contact being adjacent to the stacked body via a spacer insulating layer, and

a spacer protective layer being provided between the source contact and the spacer insulating layer and including a nitride or a metal oxide.

2. The semiconductor memory device according to claim 1 , wherein

the source contact comprises:

a first conductive layer extending in the first direction; and

a barrier metal layer provided on a side surface of the first conductive layer, and

the first conductive layer contacts the spacer protective layer via the barrier metal layer.

3. The semiconductor memory device according to claim 1 , wherein

the spacer protective layer includes silicon nitride (Si 3 N 4 ) or alumina (Al 2 O 3 ).

4. The semiconductor memory device according to claim 1 , wherein

the memory columnar body comprises:

a semiconductor layer extending in the first direction;

a tunnel insulating layer covering a side surface of the semiconductor layer; and

a charge accumulation layer covering a side surface of the tunnel insulating layer.

5. The semiconductor memory device according to claim 4 , wherein

a block insulating layer is provided between the charge accumulation layer and the control gate electrode.

6. The semiconductor memory device according to claim 5 , wherein

the stacked body comprises:

the control gate electrodes and first inter-layer insulating layers that are stacked alternately in the first direction; and

a second inter-layer insulating layer provided above the control gate electrodes and the first inter-layer insulating layers, and

the block insulating layer is provided between the second inter-layer insulating layer and the source contact.

7. The semiconductor memory device according to claim 5 , wherein

the block insulating layer is divided in the first direction.

8. A method of manufacturing a semiconductor memory device, the semiconductor memory device comprising:

a stacked body that includes a plurality of control gate electrodes stacked above a substrate;

a memory columnar body that extends in a first direction above the substrate and configures a memory string along with the stacked body; and

a source contact that extends in the first direction and is electrically connected to one end of the memory string,

the method comprising:

alternately forming a plurality of first layers and a plurality of first inter-layer insulating layers above the substrate;

forming a first opening that penetrates the plurality of first layers and the plurality of first inter-layer insulating layers;

forming the memory columnar body inside the first opening;

forming a second opening that penetrates the plurality of first layers and the plurality of first inter-layer insulating layers;

forming the stacked body that includes the plurality of control gate electrodes;

forming a spacer insulating layer that covers a side surface and bottom surface of the second opening;

forming a spacer protective layer that covers an upper surface and side surface of the spacer insulating layer;

selectively removing a portion of the spacer insulating layer and the spacer protective layer, the portion covering the bottom surface of the second opening; and

forming the source contact inside the second opening.

9. The method of manufacturing a semiconductor memory device according to claim 8 , further comprising:

forming a barrier metal layer on a side surface of the spacer protective layer before forming a first conductive layer to form the source contact along with the barrier metal layer.

10. The method of manufacturing a semiconductor memory device according to claim 8 , further comprising the following performed after the second opening has been formed and before the spacer insulating layer is formed, namely:

removing the first layer via the second opening; and

forming the plurality of control gate electrodes via the second opening.

11. The method of manufacturing a semiconductor memory device according to claim 10 , further comprising:

after the memory columnar body has been formed and before the second opening is formed, forming a second inter-layer insulating layer above the plurality of first layers and the plurality of first inter-layer insulating layers; and

after the first layer has been removed and before the plurality of control gate electrodes are formed, forming a block insulating layer on side surfaces of the first inter-layer insulating layer and the second inter-layer insulating layer, via the second opening.

12. The method of manufacturing a semiconductor memory device according to claim 11 , further comprising

forming the spacer insulating layer so as to cover the side surface of the second inter-layer insulating layer via the block insulating layer.

13. The method of manufacturing a semiconductor memory device according to claim 11 , further comprising:

after the block insulating layer has been formed and before the spacer insulating layer is formed, selectively removing a portion of the block insulating layer covering the side surface of the first inter-layer insulating layer.

14. The method of manufacturing a semiconductor memory device according to claim 8 , wherein

the first layers are conductive layers, and

the plurality of control gate electrodes is formed by forming the second opening.