Method for thermo-mechanical stress reduction in semiconductor devices and corresponding device
In one embodiment, a semiconductor device includes one or more metallizations, such as, e.g., Cu-RDL metallizations, provided on a passivation layer over a dielectric layer. A via is provided through the passivation layer and the dielectric layer in the vicinity of the corners of the metallization. The via may be a “dummy” via without electrical connections to an active device and may be provided at a distance between approximately 1 micron (10 −6 m.) and approximately 10 micron (10 −5 m.) from each one of said converging sides landing on an underlying metal layer.
1. A method, comprising:
manufacturing a semiconductor device, the manufacturing including:
providing a passivation layer over a dielectric layer, the passivation layer being formed from SiC or silicon carbide (SiC) or silicon nitride (SiN);
providing a metallization layer on the passivation layer, the metallization layer having a corner; and
providing a via through said passivation layer and said dielectric layer near said corner, a portion of the metallization layer being in the via, wherein the portion of the metallization layer in the via is shaped as a frustum with a base and a tip, wherein thicknesses of the passivation layer and the dielectric layer are such that the tip is farther from a bottom surface of the passivation layer than the base.
2. The method of claim 1 , wherein providing said via includes providing the via without electrical connections to an active device.
3. The method of claim 1 , wherein:
said corner includes converging sides; and
providing said via includes providing said via at a distance between approximately 1 micron and approximately 10 micron from each one of said converging sides.
4. The method of claim 1 , wherein the metallization layer is a Cu (copper) metallization layer.
5. The method of claim 1 , wherein providing said via includes providing the via as a via landing on an underlying metal layer in a substrate.
6. The method of claim 1 , further comprising forming a barrier layer lining the via and underlying the metallization layer.
7. A semiconductor device, comprising:
a dielectric layer;
a passivation layer over the dielectric layer, the passivation layer being an SiC layer or an SiN layer;
a metallization layer having a corner;
a plurality of vias including a via through said passivation layer and said dielectric layer near said corner, a portion of the metallization layer being in the via having a frustum shape; and
an underlying metal layer, the underlying metal layer having a plurality of landings underlying the dielectric layer, wherein each portion of the metallization layer in the plurality of vias includes a via landing on the respective landing of the underlying metal layer, wherein the metallization layer is a conductive layer configured to conduct current across the metallization layer, a first one of the plurality of landings being a dummy layer configured to restrict current across the underlying metal layer and a second one of the plurality of landings being an active layer configured to conduct current across the underlying metal layer.
8. The semiconductor device of claim 7 , wherein said via is without electrical connections to an active device.
9. The semiconductor device of claim 7 , wherein said corner includes converging sides, wherein said via is at a distance between approximately 1 micron and approximately 10 micron from each one of said converging sides.
10. The semiconductor device of claim 7 , wherein said metallization layer includes a Cu metallization layer.
11. The semiconductor device of claim 7 , further comprising a barrier layer lining the via and underlying the metallization layer.
12. A semiconductor device, comprising:
a dielectric layer;
a passivation layer over the dielectric layer, the passivation layer including at least one of SiN and SiC;
a metallization layer on the passivation layer, the metallization layer having a corner;
a via through said passivation layer and said dielectric layer near said corner, wherein the metallization layer extends into the via;
a barrier layer lining the via and extending between the metallization layer and the passivation layer; and
a capping layer over the metallization layer, the capping layer abutting the barrier layer at the corner of the metallization layer.
13. The semiconductor device of claim 12 , wherein said via is without electrical connections to an active device.
14. The semiconductor device of claim 12 , wherein said corner includes converging sides, wherein said via is at a distance between approximately 1 micron and approximately 10 micron from each one of said converging sides.
15. The semiconductor device of claim 12 , wherein said metallization layer includes a Cu metallization layer.
16. The semiconductor device of claim 12 , further comprising:
a substrate having a first planar surface, the dielectric layer on the first planar surface of the substrate; and
an underlying metal layer in the substrate and having a second planar surface coplanar with the first planar surface, the underlying metal layer underlying the dielectric layer, wherein said via includes a via landing on the underlying metal layer.