IP Library Granted Patent US 9,726,951
Granted Patent B2
US 9,726,951 · App. 15/251,531 · Granted Aug 8, 2017

Liquid crystal display device

Inventors: Takahiro Ochiai (Tokyo, JP); Motoharu Miyamoto (Tokyo, JP); Masahiro Hoshiba (Tokyo, JP)
Assignee: Japan Display Inc.
G02F1/136209G02F1/1368G02F1/13454G02F1/133512G02F1/136227G09G3/3677G09G3/3688H01L27/124H01L27/1222H01L29/78609H01L29/78633H01L29/78669G09G2300/0809G09G2310/0202
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,726,951
App. No.
15/251,531
Granted
Aug 8, 2017
Kind
B2
Abstract

A liquid crystal display device is provided with a thin film transistor which includes a gate electrode film that is provided in a first electrode layer located over a first insulating layer, a semiconductor film that is disposed over the gate electrode film via a second insulating layer, a drain electrode and a source electrode that are provided in a second electrode layer located over the semiconductor film and are in contact with an upper surface of the semiconductor film, and a light blocking film that is disposed under the first insulating layer. At least a part thereof overlaps the semiconductor film and the gate electrode film in a plan view. One of the drain electrode and the source electrode is connected to a gate line, and the light blocking film is electrically connected to the source electrode.

Claims (39)

1. A display device comprising:

a substrate;

a pixel provided on the substrate;

a pixel transistor provided in the pixel;

an image signal line supplying an image signal to the pixel transistor;

a scanning signal line that supplying a control signal to the pixel transistor; and

an output transistor provided on the substrate and outputting the control signal to the scanning signal line,

wherein the output transistor includes

a gate electrode that is provided in a first electrode layer;

a semiconductor film that is disposed above the gate electrode via an insulating layer;

a drain electrode that is provided in a second electrode layer located over the semiconductor film and is in contact with a part of an upper surface of the semiconductor film;

a source electrode that is provided in the second electrode layer over the semiconductor film and is in contact with a part of the upper surface of the semiconductor film; and

a light shielding film that is provided in the second electrode layer so that at least a part thereof overlaps the semiconductor film and the first electrode layer in a plan view,

wherein the source electrode is electrically connected to the scanning signal line, and

wherein a wiring electrically connects between the light shielding film and the source electrode, and extends in a direction that intersects the scanning signal line.

2. The display device according to claim 1 , wherein the drain electrode is connected to a clock signal line which supplies a periodic pulse.

3. The display device according to claim 1 , wherein the gate electrode is connected to the second electrode layer via a first hole which penetrates through the insulating layer.

4. The display device according to claim 2 ,

wherein the light shielding film is connected to the scanning signal line via a second hole which penetrates through the insulating layer.

5. A display device comprising:

a substrate;

a pixel formed on the substrate;

a pixel transistor formed in the pixel;

an image signal line that supplies an image signal to the pixel transistor;

a scanning signal line that supplies a control signal for controlling turning-on and turning-off of the pixel transistor; and

an output transistor that outputs the control signal to the scanning signal line,

wherein the output transistor includes

a first insulating layer that is formed on the substrate;

a gate electrode that is provided in a first electrode layer located over the first insulating layer;

a semiconductor film that is disposed above the gate electrode film via a second insulating layer;

a drain electrode that is provided in a second electrode layer located over the semiconductor film and is in contact with a part of an upper surface of the semiconductor film; and

a source electrode that is provided in the second electrode layer located over the semiconductor film and is in contact with a part of the upper surface of the semiconductor film,

a light shielding film that is provided in the second electrode layer so that a part thereof overlaps the semiconductor film and the gate electrode in a plan view,

wherein one of the drain electrode and the source electrode is connected to the scanning signal line, and

wherein a wiring electrically connects between the light shielding film and the one of the drain electrode and source electrode, and extends in a direction that intersects the scanning signal line.

6. The display device according to claim 5 , wherein the other of the drain electrode and the source electrode is connected to a clock signal line which supplies a periodic pulse.

7. The display device according to claim 5 , wherein the gate electrode is connected to the second electrode layer via a first hole which penetrates through the second insulating layer.

8. The display device according to claim 6 , wherein the gate electrode is connected to the second electrode layer via a first hole which penetrates through the second insulating layer, and

wherein the light shielding film is connected to the scanning signal line via a second hole which penetrates through the second insulating layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
Priority Claims (1)
JP 2013-018188 · Feb 1, 2013 · national
Continuity (3)
Continuation 14749132 · Jun 24, 2015
Continuation 14168062 · Jan 30, 2014
Related Publication 20160370672A1 · Dec 22, 2016