Scan circuitry with IDDQ verification

1. An integrated circuit, comprising:

a first logic circuit coupled between a first power supply terminal and a second power supply terminal, wherein the first logic circuit includes:

a first scan chain circuit including a scan output node;

a configurable defect circuit connected to the scan output node of the first scan chain circuit and having a logic node and a conductive element coupled between the logic node and the first or the second power supply terminal, wherein the scan output node is configured to, during a quiescent current testing mode, place a predetermined logic state on the logic node such that a detectable current flows through the conductive element when the integrated circuit is not defective; and

a current measurement circuit having an input coupled to an output of the configurable defect circuit and configured to detect the detectable current through the conductive element when the integrated circuit is not defective.

2. The integrated circuitry of claim 1 , wherein the first scan chain circuit is configured to receive a vector of bit values, wherein one bit value of the vector of bit values which corresponds to the scan output node results in the predetermined logic state on the logic node.

3. The integrated circuitry of claim 2 , wherein each remaining bit value of the plurality of bit values does not affect the predetermined logic state on the logic node.

4. The integrated circuitry of claim 1 , wherein the configurable defect circuit is configured to have no functional effect in the first logic circuit during a normal mode of operation.

5. The integrated circuitry of claim 4 , wherein the configurable defect circuit is configured to only be enabled during the quiescent current testing mode.

6. The integrated circuitry of claim 1 , wherein the configurable defect circuit is configured to, when the predetermined logic state is on the logic node during the quiescent current testing mode, provide a path via the conductive element between the first power supply terminal and the second power supply terminal.

7. The integrated circuitry of claim 1 , wherein the configurable defect circuit is configured to, during the quiescent current testing mode, when the predetermined logic state is not placed on the logic node, not provide a current through the conductive element.

8. The integrated circuitry of claim 1 , wherein the conductive element comprises one of a resistor or a transistor.

9. The integrated circuitry of claim 1 , further comprising a second logic circuit coupled between a third power supply terminal and a fourth power supply terminal, wherein the second logic circuit includes:

a second scan chain circuit; and

a second configurable defect circuit coupled to a scan output node of the second scan chain circuit and having a second logic node and a second conductive element coupled between the second logic node and the third or the fourth power supply terminal, wherein the scan output node of the second scan chain circuit is configured to, during the quiescent current testing mode, place a second predetermined logic state on the second logic node such that a second current flows through the second conductive element.

10. The integrated circuitry of claim 1 , wherein the first scan chain circuit comprises a plurality of flip flops, wherein the scan output node is an output of one of the plurality of flip flops.

11. The integrated circuitry of claim 1 , wherein the logic node in the configurable defect circuit comprises an inverter, the inverter including an input coupled to an output of the scan output node and an output coupled to the conductive element.

12. The integrated circuitry of claim 1 , wherein the scan output node includes a multiplexer and a flip flop circuit, the multiplexer having a first input coupled to an output of a preceding scan stage circuit in the first scan chain circuit, a second input coupled to the predetermined logic state, a select enable control input, and an output coupled to a data input of a flip flop circuit.

13. The integrated circuitry of claim 12 , further comprising an output of the flip flop circuit connected to an input of the current measurement circuit.

14. The integrated circuitry of claim 13 , further comprising a clock signal connected to a clock input of the flip flop circuit.

15. The integrated circuitry of claim 12 , further comprising:

a combination logic circuit, wherein the preceding scan stage circuit includes a multiplexer and a flip flop circuit,

the multiplexer of the preceding scan stage circuit having

a first input coupled to an output of the combinational logic circuit,

a second input coupled to an output of a second preceding scan stage circuit in the first scan chain circuit,

a select enable control input, and

an output coupled to a data input of the flip flop circuit of the preceding scan stage circuit.

16. The integrated circuitry of claim 15 , further comprising:

a first scan stage circuit in the first scan chain circuit, wherein the first scan stage circuit includes a multiplexer and a flip flop circuit,

the multiplexer of the first scan stage circuit having

a first input coupled to functional data source,

a second input coupled to receive a test vector from an output of a scan input port,

a select enable control input, and

an output coupled to a data input of the flip flop circuit of the first scan stage circuit.

17. The integrated circuitry of claim 16 , further comprising an output of the flip flop circuit of the first scan stage circuit connected to an input of a multiplexer of a subsequent scan stage circuit.

18. The integrated circuitry of claim 1 , wherein the current measurement circuit includes an inverter in the logic node and a resistor in the conductive element.

19. The integrated circuitry of claim 1 , wherein the current measurement circuit includes an inverter in the logic node and a transistor in the conductive element.