IP Library Patent Application 15253373
Patent Application
App. No. 15/253,373

STRESS RELIEF IN SEMICONDUCTOR WAFERS

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Quick Facts
Patent No.
US None
App. No.
15/253,373
Abstract

Methods for compensating for warpage in a semiconductor structure comprising an epitaxial layer grown on a semiconductor substrate. The methods include forming a buffer layer on the epitaxial layer and forming a compensating layer on the buffer layer; forming a buffer layer on the semiconductor substrate and forming a compensating layer on the buffer layer; and forming grooves in the epitaxial layer.

Claims (37)

1 ) A semiconductor wafer comprising:

a substrate of a semiconductor material having first and second major surfaces;

an epitaxial layer formed on the first surface of the substrate;

a buffer layer formed on the epitaxial layer; and

a compensating layer formed on the buffer layer and compensating for warpage in the epitaxial layer.

2 ) The semiconductor wafer of claim 1 wherein grooves are formed in the epitaxial layer to reduce its warpage.

3 ) The semiconductor wafer of claim 2 wherein the grooves are substantially parallel and aligned with the contours of the warpage.

4 ) The semiconductor wafer of claim 1 wherein one of the epitaxial layer and the compensating layer has compressive stress and the other has tensile stress.

5 ) A semiconductor wafer comprising:

a substrate of a semiconductor material having first and second major surfaces;

an epitaxial layer formed on the first surface of the substrate;

a buffer layer formed on the second surface of the substrate; and

a compensating layer formed on the buffer layer and compensating for warpage in the epitaxial layer.

6 ) The semiconductor wafer of claim 5 wherein grooves are formed in the epitaxial layer to reduce its warpage.

7 ) The semiconductor wafer of claim 6 wherein the grooves are substantially parallel and aligned with the contours of the warpage.

8 ) The semiconductor wafer of claim 5 wherein both the epitaxial layer and the compensating layer have compressive stress or both layers have tensile stress.

9 ) A semiconductor wafer comprising:

a substrate of a semiconductor material having first and second major surfaces;

an epitaxiaxial layer formed on the first surface of the substrate; and

grooves in the epitaxial layer.

10 ) A method for compensating for warpage in a semiconductor wafer comprising:

forming an epitaxial layer on a first major surface of a semiconductor wafer;

forming a buffer layer on the epitaxial layer;

forming a compensating layer on the buffer layer, the compensating layer compensating for warpage in the epitaxial layer.

11 ) The method of claim 10 further comprising forming grooves in the epitaxial layer.

12 ) The method of claim 10 wherein one of the epitaxial layer and the compensating layer has compressive stress and the other has tensile stress

13 ) A method for compensating for warpage in a semiconductor wafer comprising:

forming an epitaxial layer on a first major surface of a semiconductor wafer;

forming a buffer layer on a second major surface of the semiconductor wafer;

forming a compensating layer on the buffer layer, the compensating layer compensating for warpage in the epitaxial layer.

14 ) The method of claim 13 further comprising forming grooves in the epitaxial layer.

15 ) The method of claim 13 wherein both the epitaxial layer and the compensating layer have compressive stress or both layers have tensile stress.

16 ) A method for compensating for warpage in a semiconductor wafer comprising:

forming an epitaxial layer on a first major surface of a semiconductor wafer;

forming a buffer layer on the epitaxial layer;

forming grooves in the epitaxial layer.

17 ) The method of claim 16 wherein the grooves are substantially parallel.

Assignments (4)
PATENT RELEASE AND REASSIGNMENT Recorded Jul 5, 2022
From: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
To: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
Reel/Frame 060574/0001 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Sep 25, 2019
From: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 050484/0204 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2017
From: DOPP, DOUGLAS
To: II-VI OPTOELECTRONIC DEVICES, INC.
Reel/Frame 041793/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2017
From: CHANG, KEVIN CHI-WEN; KRYSTCK, WOJCIECH; HENSLEY, DAVID; WILKINSON, WILLIAM
To: II-VI OPTOELECTRONIC DEVICES, INC.
Reel/Frame 041758/0650 →