Integrated fan-out package and method for fabricating the same

1. A method for fabricating an integrated fan-out package, comprising:

mounting a plurality of memory devices onto a carrier, and one of the memory devices including stacked memory chips and a controller;

forming a first insulating portion of an insulation encapsulation over the carrier to encapsulate the memory devices;

mounting an integrated circuit onto the memory devices, the integrated circuit being electrically connected to the memory devices;

forming a second insulating portion of the insulation encapsulation over the first insulating portion to encapsulate the integrated circuit; and

forming a redistribution circuit structure on the insulation encapsulation and the integrated circuit, the redistribution circuit structure being electrically connected to the integrated circuit and the memory devices, wherein the integrated circuit comprises an active surface and a rear surface, the active surface or the rear surface of the integrated circuit faces the memory devices after the integrated circuit is mounted onto the memory devices.

2. The method as claimed in claim 1 further comprising:

forming a plurality of conductive pillars on the memory devices before forming the second insulating portion of the insulation encapsulation, the conductive pillars being electrically connected to the integrated circuit and the memory devices, and the conductive pillars being embedded in the second insulating portion of the insulation encapsulation and being electrically connected to the redistribution circuit structure after forming the second insulating portion of the insulation encapsulation and the redistribution circuit structure.

3. A method for fabricating integrated fan-out packages, comprising:

mounting a plurality of memory devices onto a wafer, the wafer comprising a plurality of integrated circuits formed therein, the memory devices being electrically connected to the integrated circuits in the wafer, and one of the memory devices including stacked memory chips and a controller;

forming an insulating encapsulation over the wafer to encapsulate the memory devices;

forming a redistribution circuit structure on the insulating encapsulation and the memory devices, the redistribution circuit structure being electrically connected to the integrated circuits and the memory devices; and

sawing the redistribution circuit structure, the insulating encapsulation, and the wafer to form a plurality of singulated packages, wherein the integrated circuit comprises an active surface and a rear surface, the active surface or the rear surface of the integrated circuit faces the memory devices after the integrated circuit is mounted onto the memory devices.

4. The method as claimed in claim 3 further comprising:

forming a plurality of conductive pillars on the wafer before forming the insulating encapsulation, the conductive pillars being connected to the integrated circuit, and the conductive pillars being embedded in the insulating encapsulation and being connected to the redistribution circuit structure after forming the insulating encapsulation and the redistribution circuit structure.

5. The method as claimed in claim 3 further comprising:

forming a plurality of conductive terminals electrically connected to the redistribution circuit structure, wherein the redistribution circuit structure is between the conductive terminals and the memory devices.

6. The method as claimed in claim 5 further comprising:

mounting at least one of the singulated packages onto a package circuit substrate, wherein the redistribution circuit structure in the at least one singulated package is electrically connected to the package circuit substrate through the conductive terminals.

7. An integrated fan-out package, comprising:

an integrated circuit;

a plurality of memory devices electrically connected to the integrated circuit, and one of the memory devices including stacked memory chips and a controller;

an insulating encapsulation, the integrated circuit and the memory devices being stacked, and the memory device being embedded in the insulating encapsulation; and

a redistribution circuit structure on the insulating encapsulation, the redistribution circuit structure being electrically connected to the integrated circuit and the memory devices, wherein the integrated circuit comprises an active surface and a rear surface, the active surface or the rear surface of the integrated circuit faces the memory devices after the integrated circuit is mounted onto the memory devices.

8. The package as claimed in claim 7 , wherein the stacked memory chips and the controller are electrically connected to one another through bumps.

9. The package as claimed in claim 7 , wherein the integrated circuit and the memory devices are embedded in the insulating encapsulation.

10. The package as claimed in claim 7 , wherein the integrated circuit comprises an active surface and a rear surface, the rear surface of the integrated circuit faces the memory devices, the active surface of the integrated circuit faces the redistribution circuit structure, and the integrated circuit is electrically connected to the redistribution circuit structure.

11. The package as claimed in claim 10 further comprising:

a plurality of conductive pillars embedded in the insulating encapsulation, the conductive pillars being electrically connected to the memory devices and the redistribution circuit structure; and

a redistribution layer on surfaces of the memory devices, the integrated circuit being electrically connected to the memory devices through the redistribution layer, the conductive pillars, and the redistribution layer.

12. The package as claimed in claim 7 further comprising:

a plurality of conductive terminals electrically connected to the redistribution circuit structure, wherein the redistribution circuit structure is between the conductive terminals and the memory devices.

13. The package as claimed in claim 12 further comprising:

a package circuit substrate, wherein the redistribution circuit structure is electrically connected to the package circuit substrate through the conductive terminals.

14. The package as claimed in claim 7 , wherein the integrated circuit comprises an active surface and a rear surface, the active surface of the integrated circuit faces the memory devices, and the integrated circuit is electrically connected to the memory devices through a plurality of bumps between the active surface and the memory devices.

15. The package as claimed in claim 14 further comprising a redistribution layer between the integrated circuit and the memory devices, wherein the redistribution layer is on surfaces of the memory devices, and the memory devices are electrically connected to the integrated circuit through the redistribution layer.

16. The package as claimed in claim 14 , wherein the integrated circuit is between the redistribution circuit structure and the memory devices.

17. The package as claimed in claim 16 further comprising a plurality of conductive pillars embedded in the insulating encapsulation, wherein the conductive pillars are electrically connected to the memory devices and the redistribution circuit structure.

18. The package as claimed in claim 14 , wherein the memory devices are between the redistribution circuit structure and the integrated circuit.

19. The package as claimed in claim 18 further comprising a plurality of conductive pillars embedded in the insulating encapsulation, wherein the conductive pillars are electrically connected to the integrated circuit and the redistribution circuit structure.