Slave device alert signal in inter-integrated circuit (I2C) bus system
A system having master and slave devices and communicating over an I2C bus has SDA and a SCL lines that are normally high unless a device pulls the voltage of the line Low. Normal data signals on the SDA line are set during the low phase of the clock signals on the SCL line and transferred to a receiver during the high phase of the clock signals. A slave device provides an alert signal on the SDA line during the low phase of the clock signals to send an alert signal to the master device. The alert signal may be a pulse signaling the slave device wakeup or a pulse pattern identifying the alerting slave device.
1. An inter-integrated circuit (I2C) bus system comprising:
at least one master device; and
at least one slave device communicating with the master device over a bidirectional two-line I2C bus, the I2C bus having a serial data (SDA) line and a serial clock (SCL) line that are normally high unless a device pulls the voltage of the line low,
wherein:
the master device provides clock signals having high and low phases to the SCL line;
one of the master and the slave device, as transmitter, sets normal data signals on the SDA line during the low phase of the clock signals on the SCL line and the normal data signals are transferred to the other device, as receiver, during the high phase of the clock signals on the SCL line; and
the slave device provides an alert pulse on the SDA line during the low phase of the clock signals on the SCL line to send an alert signal to the master device.
2. The I2C bus system of claim 1 , wherein the master device has an SDA detector that detects normal data signals on the SDA line during the high phase of the clock signals on the SCL line, and that detects pulses of the alert signal on the SDA line during the low phase of the clock signals on the SCL line.
3. The I2C bus system of claim 2 , wherein the slave device has a sleep mode during which elements of the slave device are non-operational, and wherein the alerting slave device provides the alert signal when exiting the sleep mode and becoming operational for receiving normal data signals.
4. The I2C bus system of claim 3 , wherein the I2C bus system comprises a single master device and a single slave device, and the master device detects an alert signal comprising a pulse on the SDA line.
5. The I2C bus system of claim 3 , wherein the master device holds the normal data signals until the master device detects the alert signal.
6. The I2C bus system of claim 2 , wherein master and slave devices that communicate over the I2C bus release the voltage of the SDA line when the SCL line changes to the low phase and an alerting slave device subsequently pulls the SDA line low to provide an alert pulse.
7. The I2C bus system of claim 6 , wherein the alerting slave device releases the SDA line after providing the alert signal.
8. The I2C bus system of claim 2 , wherein the master device communicates with a plurality of the slave devices over the I2C bus, and wherein an alerting slave device provides an alert signal comprising a succession of alert pulses that identifies the alerting slave device to the master device.
9. The I2C bus system of claim 8 , wherein the master device prioritizes communication with the alerting slave device when the master device determines the identification of the alerting device.
10. An inter-integrated circuit (I2C) slave device for an I2C bus system comprising at least one master device and at least one slave device communicating over a bidirectional two-line I2C bus, the I2C bus having a serial data (SDA) line and a serial clock (SCL) line that are normally high unless a device pulls the voltage of the line low, wherein the master device provides clock signals having high and low phases to the SCL line, and wherein a master or slave device as transmitter sets normal data signals on the SDA line during the low phase of the clock signals on the SCL line and the normal data signals are transferred to another device as receiver during the high phase of the clock signals on the SCL line, and wherein the slave device comprises:
an alert module that provides an alert pulse on the SDA line during the low phase of the clock signals on the SCL line to send an alert signal to the master device.
11. The I2C slave device of claim 10 , wherein the alert module has an SCL detector that detects the high and low phases of the clock signals on the SCL line, and an alert signal generator that provides the alert signal on the SDA line during the low phase of the clock signals on the SCL line.
12. The I2C slave device of claim 10 , wherein the slave device has a sleep mode during which elements of the slave device are non-operational, and wherein the alerting slave device provides the alert signal when exiting the sleep mode and becoming operational for receiving normal data signals.
13. The I2C slave device of claim 10 , wherein master and slave devices that communicate over the I2C bus release the voltage of the SDA line when the SCL line changes to the low phase, and wherein the slave device subsequently pulls the SDA line low to provide an alert pulse.
14. The I2C slave device of claim 13 , wherein the alerting slave device releases the SDA line after providing the alert signal.
15. The I2C slave device of claim 10 , wherein the master device communicates with a plurality of the slave devices over the I2C bus, and wherein the slave device provides an alert signal comprising a succession of alert pulses that identifies the alerting slave device to the master device and enables the master device to prioritize communication with the alerting slave device when the master device identifies the alerting slave device.
16. An inter-integrated circuit (I2C) master device for an I2C bus system comprising at least one master device and at least one slave device communicating over a bidirectional two-line I2C bus, the I2C bus having a serial data (SDA) line and a serial clock (SCL) line that are normally high unless a device pulls the voltage of the line low, wherein a master or slave device as transmitter sets normal data signals on the SDA line during a low phase of the clock signals on the SCL line and the normal data signals are transferred to another, receiver device, during a high phase of the clock signals on the SCL line, the master device comprising:
a clock module for providing clock signals having high and low phases to the SCL line;
an SDA transmit module for providing normal data signals to the SDA line during the high phase of the clock signals on the SCL line; and
an SDA detector that detects normal data signals on the SDA line during the high phase of the clock signals on the SCL line, and detects pulses of the alert signal on the SDA line during the low phase of the clock signals on the SCL line.
17. The I2C master device of claim 16 , wherein the master device holds the normal data signals until the master device detects the alert signal signaling that a slave device has exited a sleep mode during which elements of the alerting slave device are non-operational, and has become operational for receiving normal data signals.
18. The I2C master device of claim 16 , wherein the master device and any slave devices that communicate over the I2C bus release the voltage of the SDA line when the SCL line goes low, and wherein the alert detector detects an alerting slave device subsequently pulling the SDA line low to provide an alert pulse.
19. The I2C master device of claim 16 , for communicating with a plurality of the slave devices over the I2C bus, wherein the SDA detector detects and registers an alert signal comprising a succession of alert pulses that identifies an alerting slave device to the master device.
20. The I2C master device of claim 19 , wherein the master device prioritizes communication with the alerting slave device when the master device determines the identification from the succession of alert pulses.