Data processing method and apparatus for executing task code using reservation instruction and release instruction

1. A data processing method for executing a task code in a computer, the computer running an operating system to manage execution of a plurality of task codes, the operating system managing a hardware thread pool which comprises multiple hardware threads, and the method being performed by the computer using the operating system and comprising:

reading, by the operating system, a hardware thread reservation instruction preset in the task code by a compiler, the hardware thread reservation instruction comprising a hardware thread reservation request, and the hardware thread reservation request requesting the operating system to allocate a hardware thread in the hardware thread pool for executing the task code;

allocating, by the operating system, the hardware thread for executing the task code;

loading, by the operating system, the task code to the hardware thread such that the hardware thread executes the loaded task code;

obtaining an execution result from the hardware thread after the task code is executed;

reading, by the operating system, a hardware thread release instruction preset in the task code by the compiler, the hardware thread release instruction requesting the operating system to release the hardware thread in the hardware thread pool from executing the task code when the entire task code has been executed; and

releasing, by the operating system, the hardware thread from executing the task code, and

wherein the task code comprises subtask codes corresponding to multiple subtasks, the multiple subtasks needing to be executed for the task code to complete execution, a small-task start flag being preset in a start position of each subtask code, a small-task end flag being preset in an end position of each subtask code, multiple hardware threads have been allocated to multiple tasks, and loading the task code to the hardware thread comprises:

distinguishing, by the operating system, different subtask codes in the task code according to the small-task start flag and the small-task end flag for each subtask code; and

separately loading the subtask codes corresponding to different subtasks such that the multiple hardware threads execute the loaded task code concurrently.

2. The method according to claim 1 , wherein the method further comprises creating, by the operating system, a data structure, and after loading the task code to the hardware thread, the method further comprises:

receiving, by the operating system, a task code execution exception message that is from the hardware thread, the task code execution exception message indicating that an exception has occurred while processing the task code;

loading, to the data structure, an execution status of an abnormal subtask code in the hardware thread that feeds back the task code execution exception message; and

placing the data structure to which the execution status of the abnormal subtask code is loaded in a task scheduling queue of the operating system for execution, the task scheduling queue comprising a plurality of to-be-executed subtasks that are waiting to be executed by the hardware thread.

3. The method according to claim 1 , further comprising:

receiving, by the operating system, a hardware thread release request; and

releasing the hardware thread accordingly, the hardware thread release request is sent to the operating system when the hardware thread reads the hardware thread release instruction.

4. The method according to claim 2 , further comprising:

receiving, by the operating system, a hardware thread release request; and

releasing the hardware thread accordingly, the hardware thread release request being sent to the operating system when the hardware thread reads the hardware thread release instruction.

5. A computer, comprising:

a storage device configured to store a program code of an operating system for managing execution of a plurality of task codes; and

a processor coupled to the storage device and configured to execute the program code of the operating system to:

read a hardware thread reservation instruction preset in a task code by a compiler, the hardware thread reservation instruction comprising a hardware thread reservation request, and the hardware thread reservation request requesting the operating system to allocate a hardware thread in a hardware thread pool for executing the task code;

allocate the hardware thread for executing the task code;

load the task code to the hardware thread such that the hardware thread executes the loaded task code;

obtain an execution result from the hardware thread after the task code is executed;

read a hardware thread release instruction preset in the task code by the compiler, the hardware thread release instruction requesting the operating system to release the hardware thread in the hardware thread pool from executing the task code when the entire task code has been executed; and

release the hardware thread from executing the task code, and

wherein the task code comprises subtask codes corresponding to multiple subtasks, the multiple subtasks needing to be executed for the task code to complete execution, a small-task start flag being preset in a start position of each subtask code, a small-task end flag being preset in an end position of each subtask code, multiple hardware threads have been allocated to multiple tasks, and the processor further executing the program code of the operating system to:

distinguish different subtask codes in the task code according to the small-task start flag and the small-task end flag for each subtask code; and

separately load the subtask codes corresponding to different subtasks such that the multiple hardware threads execute the loaded task code concurrently.

6. The computer according to claim 5 , wherein the processor further executes the program code of the operating system to:

create a data structure;

receive a task code execution exception message from the hardware thread after loading the task code to the hardware thread, the task code execution exception message indicating that an exception has occurred while processing the task code;

load, to the data structure, an execution status of an abnormal subtask code in the hardware thread that feeds back the task code execution exception message; and

place the data structure to which the execution status of the abnormal subtask code is loaded in a task scheduling queue of the operating system for execution, the task scheduling queue comprising a plurality of to-be-executed subtasks that are waiting to be executed by the hardware thread.

7. The computer according to claim 5 , wherein the processor further executes the program code of the operating system to:

receive a hardware thread release request; and

release the hardware thread accordingly, the hardware thread release request being sent to the operating system when the hardware thread reads the hardware thread release instruction.

8. The computer according to claim 6 , wherein the processor further executes the program code of the operating system to:

receive a hardware thread release request; and

release the hardware thread accordingly, the hardware thread release request being sent to the operating system when the hardware thread reads the hardware thread release instruction.

9. The method according to claim 1 , further comprising:

notifying, by the operating system, the hardware thread of an address of the task code; and

executing, by the hardware thread, the task code according to the address of the task code.

10. The method according to claim 1 , further comprising:

recording, by the operating system, a position in the task code in which an exception occurs; and

resuming execution, by the hardware thread, of the task code according to the position in the task code in which the exception occurs.

11. The computer according to claim 5 , wherein the processor further executes the program code of the operating system to:

notify the hardware thread of an address of the task code; and

executing the task code according to the address of the task code.

12. The computer according to claim 5 , wherein the processor further executes the program code of the operating system to:

record a position in the task code in which an exception occurs; and

resume execution of the task code according to the position in the task code in which the exception occurs.