Semiconductor memory devices including a memory cell array and stepped wiring portions, and manufacturing methods thereof
A semiconductor memory device according to an embodiment includes a memory cell array that includes memory cells and a plurality of first conducting layers. The memory cells are arrayed in a three-dimensional manner. The first conducting layers are connected to the memory cells and are arrayed in a laminating direction. Stepped wiring portion includes a plurality of second conducting layers. The plurality of second conducting layers connect the first conducting layers and external circuits. At least one of the plurality of second conducting layers includes a contact formation area on a top surface thereof in the stepped wiring portion positioned on the first side portion side. Other ones of the plurality of second conducting layers includes a contact formation area on a top surface thereof in the stepped wiring portion positioned on the second side portion side.
1. A semiconductor memory device, comprising:
a memory cell array that includes a plurality of memory cells and a plurality of first conducting layers, the memory cells being arrayed in a three-dimensional manner, the first conducting layers being connected to the memory cells and being arrayed in a laminating direction;
a first stepped wiring portion disposed on a first side portion of the memory cell array;
a second stepped wiring portion disposed on a second side portion of the memory cell array, the second side portion being opposite from the first side portion across the memory cell array in a first direction when viewed in the laminating direction;
a third stepped wiring portion disposed on a third side portion of the memory cell array; and
a fourth stepped wiring portion disposed on a fourth side portion of the memory cell array, the fourth side portion being opposite from the third side portion across the memory cell array in a second direction when viewed in the laminating direction, the second direction intersecting the first direction,
wherein:
the first stepped wiring portion to the fourth stepped wiring portion include a plurality of second conducting layers that are connected to the plurality of first conducting layers;
at least one of the plurality of second conducting layers includes a contact formation area on a top surface thereof in the first stepped wiring portion;
other ones of the plurality of second conducting layers include a contact formation area on a top surface thereof in the second stepped wiring portion;
levels of the plurality of second conducting layers in the third stepped wiring portion are the same with levels of the plurality of the second conducting layers in the first stepped wiring portion in the laminating direction, or levels of the plurality of second conducting layers in the third stepped wiring portion are the same with levels of the plurality of the second conducting layers in the second stepped wiring portion in the laminating direction; and
levels of the plurality of second conducting layers in the fourth stepped wiring portion are the same with the levels of the plurality of the second conducting layers in the first stepped wiring portion in the laminating direction, or levels of the plurality of second conducting layers in the fourth stepped wiring portion are the same with the levels of the plurality of the second conducting layers in the second stepped wiring portion in the laminating direction.
2. The semiconductor memory device according to claim 1 , wherein:
the first stepped wiring portion includes the contact formation area on the even-th second conducting layers counted from an upper layer side and
the second stepper wiring portion includes the contact formation area on the odd-th second conducting layers counted from the upper layer side.
3. The semiconductor memory device according to claim 1 , wherein:
the first stepped wiring portion includes the contact formation area on the second conducting layer positioned downward of a predetermined position in the laminating direction; and
the second stepped wiring portion includes the contact formation area on the second conducting layer positioned upward of the predetermined position.
4. The semiconductor memory device according to claim 1 , wherein:
in the first stepped wiring portion, at least the one second conducting layer is covered with the second conducting layer positioned on an upper layer side thereof; and
in the second stepped wiring portion, at least the one second conducting layer is covered with the second conducting layer positioned on an upper layer side thereof.
5. The semiconductor memory device according to claim 4 , wherein:
the first stepped wiring portion includes the contact formation area on the even-th second conducting layers counted from an upper layer side; and
the second stepper wiring portion includes the contact formation area on the odd-th second conducting layers counted from the upper layer side.
6. The semiconductor memory device according to claim 4 , wherein:
the first stepped wiring portion includes the contact formation area on the second conducting layer positioned downward of a predetermined position in the laminating direction; and
the second stepper wiring portion includes the contact formation area on the second conducting layer positioned upward of the predetermined position.
7. The semiconductor memory device according to claim 1 , further comprising:
a first row decoder connected to the memory cell array via the first stepped wiring portion; and
a second row decoder connected to the memory cell array via the second stepped wiring portion.
8. The semiconductor memory device according to claim 7 , wherein:
the first stepped wiring portion includes the contact formation area on the even-th second conducting layers counted from an upper layer side; and
the second stepper wiring portion includes the contact formation area on the odd-th second conducting layers counted from the upper layer side.
9. The semiconductor memory device according to claim 7 , wherein:
the first stepped wiring portion includes the contact formation area on the second conducting layer positioned downward of a predetermined position in the laminating direction; and
the second stepper wiring portion includes the contact formation area on the second conducting layer positioned upward of the predetermined position.
10. The semiconductor memory device according to claim 1 , wherein the first stepped wiring portion to the fourth stepped wiring portion are formed so as to surround the memory cell array across a whole circumference.
11. The semiconductor memory device according to claim 10 , wherein:
the plurality of second conducting layers in the third stepped wiring portion are continuous with the plurality of the second conducting layers in the first stepped wiring portion, or the plurality of second conducting layers in the third stepped wiring portion are continuous with the plurality of the second conducting layers in the second stepped wiring portion; and
the plurality of second conducting layers in the fourth stepped wiring portion are continuous with the plurality of the second conducting layers in the first stepped wiring portion, or the plurality of second conducting layers in the fourth stepped wiring portion are continuous with the plurality of the second conducting layers in the second stepped wiring portion.
12. The semiconductor memory device according to claim 1 , wherein each of the first stepped wiring portion to the fourth stepped wiring portion is stepped downward as it goes away from the memory cell array.