LOW POWER STATE RETENTION MODE FOR PROCESSOR

1 . A method for conserving power in a computing device including a processor connected to a volatile system memory, the processor including a processing core, a plurality of always-on non-wakeup (AONW) resources, and a system memory controller, the method comprising:

receiving a request at the processor to enter a low power state retention (LPSR) mode;

saving, in the volatile system memory, control register settings for each of the AONW resources of the processor;

placing the volatile system memory in a self-refresh mode to maintain all data stored in the volatile system memory;

placing the system memory controller in a low power state; and

turning off power to the processing core and all of the AONW resources of the processor.

2 . The method of claim 1 , wherein the processor further includes an analog resource domain receiving a separate power signal from the AONW resources, the method further comprising:

turning off power to the analog resource domain of the processor.

3 . The method of claim 2 , wherein the analog resource domain includes at least one of a crystal oscillator, a phase-locked loop, an analog-digital converter, a power management unit, a low dropout regulator, a temperature sensor, or an RC oscillator.

4 . The method of claim 1 , wherein the AONW resources include at least one of a general power controller, clock control module, or system reset controller.

5 . The method of claim 1 , wherein the AONW resources include a volatile memory storing a program that is executed by the processor to place the volatile system memory in the self-refresh mode.

6 . The method of claim 1 , further comprising:

receiving a wake-up request at the processor;

resetting the AONW resources;

booting from an internal read-only memory;

restoring full power to the system memory controller;

causing the volatile system memory to exit the self-refresh mode; and

restoring the previously saved control register settings for each of the AONW resources.

7 . The method of claim 1 , wherein the processor is a system-on-chip.

8 . A computing device, comprising:

a volatile system memory; and

a processor connected to the volatile system memory, the processor including a processing core, a plurality of always-on non-wakeup (AONW) resources, and a system memory controller, the processor being configured to:

receive a request to enter a low power state retention (LPSR) mode,

save, in the volatile system memory, control register settings for each of the AONW resources,

place the volatile system memory in a self-refresh mode to maintain all data stored in the volatile system memory,

place the system memory controller in a low power state, and

turn off power to the processing core and all of the AONW resources.

9 . The device of claim 8 , wherein the processor further includes an analog resource domain receiving a separate power signal from the AONW resources, the processor being further configured to turn off power to the analog resource domain.

10 . The device of claim 9 , wherein the analog resource domain includes at least one of a crystal oscillator, a phase-locked loop, an analog-digital converter, a power management unit, a low dropout regulator, a temperature sensor, or an RC oscillator.

11 . The device of claim 8 , wherein the AONW resources include at least one of a general power controller, clock control module, or system reset controller.

12 . The device of claim 8 , wherein the AONW resources include a volatile memory storing a program that is executed by the processor to place the volatile system memory in the self-refresh mode.

13 . The device of claim 8 , wherein the processor is further configured to:

receive a wake-up request,

reset the AONW resources,

boot from an internal read-only memory,

restore full power to the system memory controller,

cause the volatile system memory to exit the self-refresh mode, and

restore the previously saved control register settings for each of the AONW resources.

14 . The device of claim 8 , wherein the processor is a system-on-chip.

15 . The device of claim 8 , wherein the volatile system memory is a dynamic random access memory (DRAM).