IP Library › Granted Patent US 9,711,421

Granted Patent B1

US 9,711,421 · App. 15/258,432 · Granted Jul 18, 2017

Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of GATE-snake-open-configured, NCEM-enabled fill cells

Inventors: Stephen Lam (Freemont, CA); Dennis Ciplickas (San Jose, CA); Tomasz Brozek (Morgan Hill, CA); Jeremy Cheng (San Jose, CA); Simone Comensoli (Darfo Boario Terme, IT); Indranil De (Mountain View, CA); Kelvin Doong (Hsinchu, TW); Hans Eisenmann (Tutzing, DE); Timothy Fiscus (New Galilee, PA); Jonathan Haigh (Pittsburgh, PA); Christopher Hess (Belmont, CA); John Kibarian (Los Altos Hills, CA); Sherry Lee (Monte Sereno, CA); Marci Liao (Santa Clara, CA); Sheng-Che Lin (Hsinchu, TW); Hideki Matsuhashi (Santa Clara, CA); Kimon Michaels (Monte Sereno, CA); Conor O'Sullivan (Campbell, CA); Markus Rauscher (Munich, DE); Vyacheslav Rovner (Pittsburgh, PA); Andrzej Strojwas (Pittsburgh, PA); Marcin Strojwas (Pittsburgh, PA); Carl Taylor (Pittsburgh, PA); Rakesh Vallishayee (Dublin, CA); Larg Weiland (Hollister, CA); Nobuharu Yokoyama (Tokyo, JP)

Assignee: PDF Solutions, Inc.

H01L22/20

View Patent ↗

Loading inventors, assignments & file history…

Monitor This Case

Get email alerts when status or documents change.

Order Certified Copies

Most orders are placed with the USPTO same day — all within 24 business hours.

Order via The Patent Place →

Pre-filled with this patent's details

Quick Facts

Patent No.: US 9,711,421
App. No.: 15/258,432
Granted: Jul 18, 2017
Kind: B1

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

Improved processes for manufacturing wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (“NCEM”) of fill cells that contain structures configured to target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes, including GATE-snake-open and/or GATE-snake-resistance failure modes. Such processes may involve evaluating Designs of Experiments (“DOEs”), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).

Claims (222)

1. A method for making an integrated circuit (IC), comprising at least the following:

(a) performing initial processing steps on a semiconductor wafer, said initial processing steps including:

patterning a mix of at least a thousand logic cells and fill cells;

said patterning including instantiating at least a first Design of Experiments (DOE), said first DOE comprising at least first and second GATE-snake-open-configured, non-contact electrical measurement (NCEM)-enabled fill cells, wherein each of said GATE-snake-open-configured, NCEM-enabled fill cells:

(i) contains at least one GATE snake feature;

(ii) is geometrically compatible for abutment with said logic cells; and,

(iii) is configured to present an open circuit or excessive resistance in its GATE snake feature(s) as an abnormal condition on a NCEM pad contained within the fill cell, said abnormal condition detectable by voltage contrast (VC) inspection of the pad; and,

wherein the first and second GATE-snake-open-configured, NCEM-enabled fill cells of the first DOE differ in terms of their respective probabilities of detecting an open circuit or excessive resistance in their respective GATE snake feature(s);

(b) determining a presence or absence of an open circuit or excessive resistance in a GATE snake feature by:

performing a voltage contrast examination of GATE-snake-open-configured, NCEM-enabled fill cells in the first DOE; and,

determining whether NCEMs of pads contained in the GATE-snake-open-configured, NCEM-enabled fill cells of said first DOE represent instance(s) of GATE snake open or excessive resistance failure(s); and,

(c) based, at least in part, on results from step (b), selectively performing additional processing, metrology or inspection step(s) on said wafer, and/or on other wafer(s) currently being manufactured using a process flow(s) relevant to the observed failure(s).

2. A method, as defined in claim 1 , wherein the first and second GATE-snake-open-configured, NCEM-enabled fill cells differ at least in terms of the lengths of their respective snakes.

3. A method, as defined in claim 2 , wherein the first and second GATE-snake-open-configured, NCEM-enabled fill cells differ essentially only in terms of the lengths of their respective snakes.

4. A method, as defined in claim 1 , wherein instantiating the first DOE includes forming the NCEM pad in at least one of the GATE-snake-open-configured, NCEM-enabled fill cells by patterning an enlarged metallic feature.

5. A method, as defined in claim 1 , wherein instantiating the first DOE includes forming the NCEM pad in at least one of the GATE-snake-open-configured, NCEM-enabled fill cells by patterning at least three parallel, adjacent, elongated features extending in a first direction in a first conductive layer.

6. A method, as defined in claim 5 , wherein forming the NCEM pad in the at least one of the GATE-snake-open-configured, NCEM-enabled fill cells further includes patterning at least three parallel, adjacent, elongated features extending in a second direction in a second conductive layer, the second direction being perpendicular to the first direction, the first-layer and second-layer elongated features collectively defining a rectangular mesh pad area.

7. A method, as defined in claim 6 , wherein the first-layer features are GATECNT features and the second-layer features are AACNT features.

8. A method, as defined in claim 6 , wherein forming the NCEM pad in the at least one of the GATE-snake-open-configured, NCEM-enabled fill cells further includes patterning at least three vias within the mesh pad area.

9. A method, as defined in claim 8 , wherein forming the NCEM pad in the at least one of the GATE-snake-open-configured, NCEM-enabled fill cells further includes patterning an enlarged metallic feature covering a majority of the mesh pad area.

10. A method, as defined in claim 1 , wherein determining whether NCEMs of pads contained in the GATE-snake-open-configured, NCEM-enabled fill cells of said first DOE represent instance(s) of GATE snake open or excessive resistance failure(s) further comprises determining whether the first and second GATE-snake-open-configured, NCEM-enabled fill cells exhibit different NCEM responses.

11. A method, as defined in claim 1 , wherein instantiating the first DOE involves patterning a multiplicity of GATE-snake-open-configured, NCEM-enabled fill cells irregularly within standard cell logic regions of the IC.

12. A method, as defined in claim 1 , wherein instantiating the first DOE involves patterning a multiplicity of GATE-snake-open-configured, NCEM-enabled fill cells within test block portions of standard cell logic regions of the IC.

13. A method, as defined in claim 1 , wherein instantiating the first DOE involves patterning a multiplicity of GATE-snake-open-configured, NCEM-enabled fill cells within fill cell-only regions, positioned between standard cell logic regions of the IC.

14. A method, as defined in claim 1 , wherein the first and second GATE-snake-open, NCEM-enabled fill cells differ from each other only in the position, size, or shape of a single mask-patterned feature.

15. A method, as defined in claim 1 , further comprising instantiating a second DOE, said second DOE comprising at least third and fourth NCEM-enabled fill cells.

16. A method, as defined in claim 15 , wherein the third and fourth NCEM-enabled fill cells include short structures in a tip-to-tip configuration.

17. A method, as defined in claim 15 , wherein the third and fourth NCEM-enabled fill cells include short structures in a tip-to-side configuration.

18. A method, as defined in claim 15 , wherein the third and fourth NCEM-enabled fill cells include short structures in a side-to-side configuration.

19. A method, as defined in claim 15 , wherein the third and fourth NCEM-enabled fill cells include short structures in an interlayer overlap configuration.

20. A method, as defined in claim 15 , wherein the third and fourth NCEM-enabled fill cells are selected from the list consisting of:

AA-tip-to-tip-short-configured, NCEM-enabled fill cells;

AACNT-tip-to-tip-short-configured, NCEM-enabled fill cells;

AACNT-AA-tip-to-tip-short-configured, NCEM-enabled fill cells;

TS-tip-to-tip-short-configured, NCEM-enabled fill cells;

GATE-tip-to-tip-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-tip-to-tip-short-configured, NCEM-enabled fill cells;

GATECNT-tip-to-tip-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-tip-to-tip-short-configured, NCEM-enabled fill cells;

M1-tip-to-tip-short-configured, NCEM-enabled fill cells;

V0-tip-to-tip-short-configured, NCEM-enabled fill cells;

M1-V0-tip-to-tip-short-configured, NCEM-enabled fill cells;

V1-M1-tip-to-tip-short-configured, NCEM-enabled fill cells;

V1-tip-to-tip-short-configured, NCEM-enabled fill cells;

M2-tip-to-tip-short-configured, NCEM-enabled fill cells;

M2-V1-tip-to-tip-short-configured, NCEM-enabled fill cells;

V2-M2-tip-to-tip-short-configured, NCEM-enabled fill cells;

M3-tip-to-tip-short-configured, NCEM-enabled fill cells;

V2-tip-to-tip-short-configured, NCEM-enabled fill cells;

M3-V2-tip-to-tip-short-configured, NCEM-enabled fill cells;

AA-tip-to-side-short-configured, NCEM-enabled fill cells;

AACNT-tip-to-side-short-configured, NCEM-enabled fill cells;

AACNT-AA-tip-to-side-short-configured, NCEM-enabled fill cells;

GATE-AA-tip-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-tip-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells;

TS-GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-tip-to-side-short-configured, NCEM-enabled fill cells;

M1-tip-to-side-short-configured, NCEM-enabled fill cells;

V0-tip-to-side-short-configured, NCEM-enabled fill cells;

M1-V0-tip-to-side-short-configured, NCEM-enabled fill cells;

V1-M1-tip-to-side-short-configured, NCEM-enabled fill cells;

V1-tip-to-side-short-configured, NCEM-enabled fill cells;

M2-tip-to-side-short-configured, NCEM-enabled fill cells;

M2-V1-tip-to-side-short-configured, NCEM-enabled fill cells;

V2-M2-tip-to-side-short-configured, NCEM-enabled fill cells;

M3-tip-to-side-short-configured, NCEM-enabled fill cells;

V2-tip-to-side-short-configured, NCEM-enabled fill cells;

M3-V2-tip-to-side-short-configured, NCEM-enabled fill cells;

AA-side-to-side-short-configured, NCEM-enabled fill cells;

AACNT-side-to-side-short-configured, NCEM-enabled fill cells;

AACNT-AA-side-to-side-short-configured, NCEM-enabled fill cells;

AACNT-GATE-side-to-side-short-configured, NCEM-enabled fill cells;

GATE-side-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-side-to-side-short-configured, NCEM-enabled fill cells;

TS-GATE-side-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-side-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-side-to-side-short-configured, NCEM-enabled fill cells;

M1-side-to-side-short-configured, NCEM-enabled fill cells;

V0-side-to-side-short-configured, NCEM-enabled fill cells;

M1-V0-side-to-side-short-configured, NCEM-enabled fill cells;

V1-M1-side-to-side-short-configured, NCEM-enabled fill cells;

V1-side-to-side-short-configured, NCEM-enabled fill cells;

M2-side-to-side-short-configured, NCEM-enabled fill cells;

M2-V1-side-to-side-short-configured, NCEM-enabled fill cells;

V2-M2-side-to-side-short-configured, NCEM-enabled fill cells;

M3-side-to-side-short-configured, NCEM-enabled fill cells;

V2-side-to-side-short-configured, NCEM-enabled fill cells;

M3-V2-side-to-side-short-configured, NCEM-enabled fill cells;

AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

AACNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

AACNT-AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATE-AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATE-TS-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATECNT-AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATECNT-TS-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V0-AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V0-TS-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V0-AACNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V0-GATE-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V0-GATECNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M1-AACNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M1-GATECNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M1-V0-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V1-M1-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V1-V0-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M2-M1-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M2-V1-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V2-V1-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V2-M2-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M3-M2-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M3-V2-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

AA-diagonal-short-configured, NCEM-enabled fill cells;

TS-diagonal-short-configured, NCEM-enabled fill cells;

AACNT-diagonal-short-configured, NCEM-enabled fill cells;

AACNT-AA-diagonal-short-configured, NCEM-enabled fill cells;

GATE-diagonal-short-configured, NCEM-enabled fill cells;

GATE-AACNT-diagonal-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-diagonal-short-configured, NCEM-enabled fill cells;

GATECNT-diagonal-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-diagonal-short-configured, NCEM-enabled fill cells;

M1-diagonal-short-configured, NCEM-enabled fill cells;

V0-diagonal-short-configured, NCEM-enabled fill cells;

M1-V0-diagonal-short-configured, NCEM-enabled fill cells;

V1-M1-diagonal-short-configured, NCEM-enabled fill cells;

V1-diagonal-short-configured, NCEM-enabled fill cells;

M2-diagonal-short-configured, NCEM-enabled fill cells;

M2-V1-diagonal-short-configured, NCEM-enabled fill cells;

M3-diagonal-short-configured, NCEM-enabled fill cells;

V2-M2-diagonal-short-configured, NCEM-enabled fill cells;

V2-diagonal-short-configured, NCEM-enabled fill cells;

M3-V2-diagonal-short-configured, NCEM-enabled fill cells;

AA-corner-short-configured, NCEM-enabled fill cells;

AACNT-corner-short-configured, NCEM-enabled fill cells;

AACNT-AA-corner-short-configured, NCEM-enabled fill cells;

GATE-corner-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-corner-short-configured, NCEM-enabled fill cells;

GATECNT-TS-corner-short-configured, NCEM-enabled fill cells;

GATECNT-corner-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-corner-short-configured, NCEM-enabled fill cells;

M1-corner-short-configured, NCEM-enabled fill cells;

V0-corner-short-configured, NCEM-enabled fill cells;

M1-V0-corner-short-configured, NCEM-enabled fill cells;

V1-M1-corner-short-configured, NCEM-enabled fill cells;

V1-corner-short-configured, NCEM-enabled fill cells;

M2-corner-short-configured, NCEM-enabled fill cells;

M2-V1-corner-short-configured, NCEM-enabled fill cells;

M3-corner-short-configured, NCEM-enabled fill cells;

V2-M2-corner-short-configured, NCEM-enabled fill cells;

V2-corner-short-configured, NCEM-enabled fill cells;

M3-V2-corner-short-configured, NCEM-enabled fill cells;

GATE-AA-interlayer-overlap-short-configured, NCEM-enabled fill cells;

GATE-AACNT-interlayer-overlap-short-configured, NCEM-enabled fill cells;

GATE-TS-interlayer-overlap-short-configured, NCEM-enabled fill cells;

GATECNT-TS-interlayer-overlap-short-configured, NCEM-enabled fill cells;

GATECNT-AA-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V0-AA-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V0-AACNT-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V0-TS-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V0-GATE-interlayer-overlap-short-configured, NCEM-enabled fill cells;

M1-GATECNT-interlayer-overlap-short-configured, NCEM-enabled fill cells;

M1-AACNT-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V1-V0-interlayer-overlap-short-configured, NCEM-enabled fill cells;

M2-M1-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V2-V1-interlayer-overlap-short-configured, NCEM-enabled fill cells;

M3-M2-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V0-GATECNT-via-chamfer-short-configured, NCEM-enabled fill cells;

V0-AACNT-via-chamfer-short-configured, NCEM-enabled fill cells;

V1-M1-via-chamfer-short-configured, NCEM-enabled fill cells;

V2-M2-via-chamfer-short-configured, NCEM-enabled fill cells;

V0-merged-via-short-configured, NCEM-enabled fill cells;

V1-merged-via-short-configured, NCEM-enabled fill cells;

V2-merged-via-short-configured, NCEM-enabled fill cells;

AA-snake-open-configured, NCEM-enabled fill cells;

TS-snake-open-configured, NCEM-enabled fill cells;

AACNT-snake-open-configured, NCEM-enabled fill cells;

GATECNT-snake-open-configured, NCEM-enabled fill cells;

V0-snake-open-configured, NCEM-enabled fill cells;

M1-snake-open-configured, NCEM-enabled fill cells;

V1-snake-open-configured, NCEM-enabled fill cells;

M2-snake-open-configured, NCEM-enabled fill cells;

V2-snake-open-configured, NCEM-enabled fill cells;

M3-snake-open-configured, NCEM-enabled fill cells;

AA-stitch-open-configured, NCEM-enabled fill cells;

TS-stitch-open-configured, NCEM-enabled fill cells;

AACNT-stitch-open-configured, NCEM-enabled fill cells;

GATECNT-stitch-open-configured, NCEM-enabled fill cells;

V0-stitch-open-configured, NCEM-enabled fill cells;

M1-stitch-open-configured, NCEM-enabled fill cells;

V1-stitch-open-configured, NCEM-enabled fill cells;

M2-stitch-open-configured, NCEM-enabled fill cells;

V2-stitch-open-configured, NCEM-enabled fill cells;

M3-stitch-open-configured, NCEM-enabled fill cells;

AACNT-TS-via-open-configured, NCEM-enabled fill cells;

AACNT-AA-via-open-configured, NCEM-enabled fill cells;

TS-AA-via-open-configured, NCEM-enabled fill cells;

GATECNT-GATE-via-open, NCEM-enabled fill cells;

V0-GATECNT-via-open-configured, NCEM-enabled fill cells;

V0-AA-via-open-configured, NCEM-enabled fill cells;

V0-TS-via-open-configured, NCEM-enabled fill cells;

V0-AACNT-via-open-configured, NCEM-enabled fill cells;

V0-GATE-via-open-configured, NCEM-enabled fill cells;

V0-via-open-configured, NCEM-enabled fill cells;

M1-V0-via-open-configured, NCEM-enabled fill cells;

V1-M1-via-open-configured, NCEM-enabled fill cells;

V1-M2-via-open-configured, NCEM-enabled fill cells;

M1-GATECNT-via-open-configured, NCEM-enabled fill cells;

M1-AACNT-via-open-configured, NCEM-enabled fill cells;

V2-M2-via-open-configured, NCEM-enabled fill cells;

V2-M3-via-open-configured, NCEM-enabled fill cells;

M1-metal-island-open-configured, NCEM-enabled fill cells;

M2-metal-island-open-configured, NCEM-enabled fill cells;

M3-metal-island-open-configured, NCEM-enabled fill cells;

V0-merged-via-open-configured, NCEM-enabled fill cells;

V0-AACNT-merged-via-open-configured, NCEM-enabled fill cells;

V0-GATECNT-merged-via-open-configured, NCEM-enabled fill cells;

V1-merged-via-open-configured, NCEM-enabled fill cells;

V2-merged-via-open-configured, NCEM-enabled fill cells;

V1-M1-merged-via-open-configured, NCEM-enabled fill cells; and,

V2-M2-merged-via-open-configured, NCEM-enabled fill cells.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 10, 2016

From: LAM, STEPHEN; CIPLICKAS, DENNIS; BROZEK, TOMASZ; CHENG, JEREMY; COMENSOLI, SIMONE; DE, INDRANIL; DOONG, KELVIN; EISENMANN, HANS; FISCUS, TIMOTHY; HAIGH, JONATHAN; HESS, CHRISTOPHER; KIBARIAN, JOHN; LEE, SHERRY; LIAO, MARCI; LIN, SHENG-CHE; MATSUHASHI, HIDEKI; MICHAELS, KIMON; O'SULLIVAN, CONOR; RAUSCHER, MARKUS; ROVNER, VYACHESLAV; STROJWAS, ANDRZEJ; STROJWAS, MARCIN; TAYLOR, CARL; VALLISHAYEE, RAKESH; WEILAND, LARG; YOKOYAMA, NOBUHARU

To: PDF SOLUTIONS, INC.

Reel/Frame 039975/0427 →

Continuity (5)

Continuation 15090256 · Apr 4, 2016

Continuation 15090267 · Apr 4, 2016

Continuation 15090274 · Apr 4, 2016

Continuation 15188027 · Jun 21, 2016

Provisional Application 62268463 · Dec 16, 2015