IP Library Assignment 039975/0427
Patent Assignment
Reel/Frame 039975/0427

Assignment of Assignor's Interest

Recorded: 2016-10-10 Pages: 18
Assignors
LAM, STEPHEN
Executed: 2016-04-21
CIPLICKAS, DENNIS
Executed: 2016-04-15
BROZEK, TOMASZ
Executed: 2016-04-20
CHENG, JEREMY
Executed: 2016-05-06
COMENSOLI, SIMONE
Executed: 2016-04-13
DE, INDRANIL
Executed: 2016-04-12
DOONG, KELVIN
Executed: 2016-04-28
EISENMANN, HANS
Executed: 2016-04-26
FISCUS, TIMOTHY
Executed: 2016-04-13
HAIGH, JONATHAN
Executed: 2016-04-13
HESS, CHRISTOPHER
Executed: 2016-04-12
KIBARIAN, JOHN
Executed: 2016-04-18
LEE, SHERRY
Executed: 2016-04-14
LIAO, MARCI
Executed: 2016-04-15
LIN, SHENG-CHE
Executed: 2016-04-28
MATSUHASHI, HIDEKI
Executed: 2016-04-25
MICHAELS, KIMON
Executed: 2016-04-18
O'SULLIVAN, CONOR
Executed: 2016-04-21
RAUSCHER, MARKUS
Executed: 2016-04-26
ROVNER, VYACHESLAV
Executed: 2016-04-13
STROJWAS, ANDRZEJ
Executed: 2016-04-28
STROJWAS, MARCIN
Executed: 2016-04-13
TAYLOR, CARL
Executed: 2016-04-13
VALLISHAYEE, RAKESH
Executed: 2016-04-12
WEILAND, LARG
Executed: 2016-04-21
YOKOYAMA, NOBUHARU
Executed: 2016-04-13
Assignee
PDF SOLUTIONS, INC.
333 W. SAN CARLOS ST., STE 1000, SAN JOSE, CALIFORNIA, 95110
Covered Properties (5)
Process for Making Semiconductor Dies, Chips, and Wafers Using In-Line Measurements Obtained From DOEs of GATE-Snake-Open-Configured, NCEM-enabled Fill Cells
Patent: 9,711,421 →
Application: 15/258,432 →
Process for Making and Using Mesh-Style NCEM Pads
Patent: 9,911,649 →
Application: 15/259,309 →
Process for Making Semiconductor Dies, Chips, and Wafers Using Non-Contact Measurements Obtained From DOEs of NCEM-enabled Fill Cells on Test Wafers that Include Multiple Means/Steps for Enabling NC Detection of V0 Via Opens
Patent: 9,905,487 →
Application: 15/278,344 →
Process for Making Semiconductor Dies, Chips, and Wafers Using Non-Contact Measurements Obtained From DOEs of NCEM-enabled Fill Cells on Test Wafers that Include Multiple Means/Steps for Enabling NC Detection of GATECNT-GATE Via Opens
Patent: 9,953,889 →
Application: 15/281,491 →
Process for Making Semiconductor Dies, Chips, and Wafers Using Non-Contact Measurements Obtained From DOEs of NCEM-enabled Fill Cells on Test Wafers that Include Multiple Means/Steps for Enabling NC Detection of AACNT-TS Via Opens
Patent: 9,870,966 →
Application: 15/281,508 →