Process for making and using mesh-style NCEM pads
View Patent ↗Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). Such NCEM-enabled fill cells may target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes, and may include NCEM pads that comprise a mesh of GATECNT and AACNT stripes. Such wafers, chips, or dies may include Designs of Experiments (“DOEs”), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).
1. A method for processing a semiconductor substrate, comprising at least the following steps:
using one or more mask(s) to pattern a plurality of adjacent source/drain contact (AACNT) stripes on the substrate;
using one or more mask(s) to pattern a plurality of adjacent gate contact (GATECNT) stripes on the substrate;
wherein the GATECNT stripes perpendicularly intersect the AACNT stripes to form a mesh-style non-contact electrical measurement (NCEM) pad; and
after forming the NCEM pad, obtaining in-line NCEM from the mesh-style NCEM pad.
2. A method for processing a semiconductor substrate, as defined in claim 1 , further comprising at least the following additional steps:
using one or more mask(s) to pattern a plurality of via to interconnect stack (V0) vias above at least some of the GATECNT and/or AACNT stripes of the mesh-style NCEM pad; and,
using one or more mask(s) to pattern one or more first wiring layer (M1) features above one or more of said V0 vias to form an M1 NCEM pad.
3. A method for processing a semiconductor substrate, as defined in claim 2 , further comprising at least the following additional step:
obtaining in-line NCEM from the M1 NCEM pad.