IP Library Granted Patent US 9,991,208
Granted Patent B2
US 9,991,208 · App. 15/260,629 · Granted Jun 5, 2018

Susceptor for holding a semiconductor wafer having an orientation notch, a method for depositing a layer on a semiconductor wafer, and semiconductor wafer

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,991,208
App. No.
15/260,629
Granted
Jun 5, 2018
Kind
B2
Abstract

A semiconductor wafer processing susceptor for holding a wafer having an orientation notch during deposition of a layer on the wafer, having a placement surface for supporting the semiconductor wafer in the rear edge region of the wafer, the placement surface having a stepped outer delimitation, and an indentation of the outer delimitation of the placement surface for placement of the partial region of the edge region of the rear side of the wafer in which the orientation notch is located onto a partial region of the placement surface delimited by the indentation of the outer delimitation of the placement surface. The susceptor is used in a method for depositing a layer on a wafer having an orientation notch, and wafers made of monocrystalline silicon upon which layers are deposited using the susceptor have greater local flatness on both front and rear sides proximate the orientation notch.

Claims (4)

1. A semiconductor wafer comprising monocrystalline silicon having a diameter, a front side, a rear side, an edge region, an orientation notch in the edge region, and a deposited epitaxial layer comprising silicon on the front side, wherein the epitaxial layer has a thickness of not less than 1.5 μm and not greater than 5 μm, the semiconductor wafer having a local flatness in a region of the orientation notch, expressed by ESFQR, of not less than 5 nm and not greater than 20 nm.

2. The semiconductor wafer of claim 1 , which has a diameter of not less than 200 mm.

3. The semiconductor wafer of claim 1 , with a material deposition on the rear side of the semiconductor wafer on a rectangular evaluation area enclosing the orientation notch, wherein the thickness of the material deposition is not greater than 15 nm.

4. The semiconductor wafer of claim 2 , with a material deposition on the rear side of the semiconductor wafer on a rectangular evaluation area enclosing the orientation notch, wherein the thickness of the material deposition is not greater than 15 nm.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE DATE OF THE CHANGE OF ADDRESS FROM 03/12/2020 TO 12/03/2020 PREVIOUSLY RECORDED AT REEL: 056719 FRAME: 0881. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 1, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 057561/0451 →
CHANGE OF ADDRESS Recorded Jun 30, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 056719/0881 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2016
From: SCHAUER, REINHARD; HAGER, CHRISTIAN
To: SILTRONIC AG
Reel/Frame 039684/0119 →