Semiconductor memory device
According to an embodiment, a semiconductor memory device comprises control gate electrodes, a first semiconductor layer, a gate insulating layer, a first contact, a second semiconductor layer, a second contact, and a first conductive layer. The control gate electrodes are stacked above a substrate. The first semiconductor layer faces the control gate electrodes. The gate insulating layer is provided between the control gate electrode and the first semiconductor layer. The first contact is connected to an upper end of the first semiconductor layer. The second contact is connected to a lower end of the first semiconductor layer via the second semiconductor layer. The first conductive layer is provided above the second contact. Moreover, an end of the first conductive layer closest to the first contact is closer to the first contact than an end of the second contact closest to the first contact.
1. A semiconductor memory device, comprising:
a plurality of control gate electrodes stacked in a first direction above a substrate;
a first semiconductor layer that extends in the first direction and faces the plurality of control gate electrodes;
a gate insulating layer provided between the control gate electrode and the first semiconductor layer;
a first contact connected to an upper end of the first semiconductor layer;
a second semiconductor layer connected to a lower end of the first semiconductor layer and extending in a second direction intersecting the first direction;
a second contact connected to the second semiconductor layer at its lower end and extending in the first direction, an upper end of the second contact being further from the substrate than an upper surface of the second semiconductor layer; and
a first conductive layer provided above the second contact, an upper surface of the first conductive layer being nearer to the substrate than an upper end of the first contact and a lower surface of the first conductive layer being further from the substrate than a lower end of the first contact, wherein
in the second direction, an end of the first conductive layer closest to the first contact is positioned on a closer side to the first contact than an end of the second contact closest to the first contact, and
the first conductive layer and the second contact are not connected to each other.
2. The semiconductor memory device according to claim 1 , wherein
the first contact comprises:
a first portion connected to the upper end of the first semiconductor layer; and
a second portion provided above the first portion, and
the first portion contacts an end of the first conductive layer from the second direction.
3. The semiconductor memory device according to claim 2 , wherein the second portion contacts the upper surface of the first conductive layer from the first direction.
4. The semiconductor memory device according to claim 3 , wherein a width of the first portion in the second direction is smaller than a width of the second portion in the second direction.
5. The semiconductor memory device according to claim 1 , wherein
the control gate electrode and the second contact extend in a third direction intersecting the first and second directions,
pluralities of the first semiconductor layers and the first contacts are arranged at a first pitch along the third direction, and
a plurality of the first conductive layers are arranged at the first pitch along the third direction.
6. The semiconductor memory device according to claim 5 , wherein the plurality of first conductive layers are divided in the third direction.
7. The semiconductor memory device according to claim 1 , further comprising:
a third contact connected to the control gate electrode and extending in the first direction; and
a second conductive layer connected to an upper end of the third contact,
wherein a height of an upper surface of the second conductive layer is equal to a height of an upper surface of the first conductive layer.
8. The semiconductor memory device according to claim 1 , wherein the second semiconductor layer is the substrate.
9. A semiconductor memory device, comprising:
a plurality of control gate electrodes stacked in a first direction above a substrate;
a first semiconductor layer that extends in the first direction and faces the plurality of control gate electrodes;
a gate insulating layer provided between the control gate electrode and the first semiconductor layer;
a first contact connected to an upper end of the first semiconductor layer;
a second semiconductor layer connected to a lower end of the first semiconductor layer and extending in a second direction intersecting the first direction;
a second contact connected to the second semiconductor layer at its lower end and extending in the first direction, an upper end of the second contact being further from the substrate than an upper surface of the second semiconductor layer; and
a first conductive layer provided above the second contact, an upper surface of the first conductive layer being nearer to the substrate than an upper end of the first contact and a lower surface of the first conductive layer being further from the substrate than a lower end of the first contact, wherein
the first conductive layer contacts the first contact from the second direction, and
the first conductive layer and the second contact are not connected to each other.
10. The semiconductor memory device according to claim 9 , wherein
the first contact comprises:
a first portion connected to the upper end of the first semiconductor layer; and
a second portion provided above the first portion, and
the first portion contacts an end of the first conductive layer from the second direction.
11. The semiconductor memory device according to claim 10 , wherein the second portion contacts the upper surface of the first conductive layer from the first direction.
12. The semiconductor memory device according to claim 11 , wherein a width of the first portion in the second direction is smaller than a width of the second portion in the second direction.
13. The semiconductor memory device according to claim 9 , wherein
the control gate electrode and the second contact extend in a third direction intersecting the first and second directions,
pluralities of the first semiconductor layers and the first contacts are arranged at a first pitch along the third direction, and
a plurality of the first conductive layers are arranged at the first pitch along the third direction.
14. The semiconductor memory device according to claim 13 , wherein the plurality of first conductive layers are divided in the third direction.
15. The semiconductor memory device according to claim 9 , further comprising:
a third contact connected to the control gate electrode and extending in the first direction; and
a second conductive layer connected to an upper end of the third contact,
wherein a height of an upper surface of the second conductive layer is equal to a height of the upper surface of the first conductive layer.
16. The semiconductor memory device according to claim 9 , wherein the second semiconductor layer is the substrate.