Methods and apparatus for error detection in an imaging system

1. A system for detecting errors in image data, comprising: a pixel array comprising a plurality of pixels configured to capture an image and generate an image frame comprising a frame of pixel data;

an image processing unit, coupled to the pixel array and configured to receive the frame of pixel data generated by the pixels, comprising:

an error detection circuit configured to detect an error condition based on a count value corresponding to individual pixel data transmissions from the frame of pixel data;

wherein the image processing unit initiates a process to capture and receive new pixel data in response to at the detected error condition; and

an embedded system coupled to the image processing unit to receive output data from the image processing unit,

wherein the error detection circuit comprises: a register configured to store a predetermined value, wherein the predetermined value is greater than the number of pixels in the pixel array;

an N-bit counter connected to the reaister and configured to receive the predetermined value and generate N bits that represent the count value; and

a logic circuit connected to an output terminal of the N-bit counter and configured to receive each bit of the N-bit count value individually and generate a single output signal according to each bit.

2. The system of claim 1 , wherein the error detection circuit comprises:

a clock for generating clock cycles, wherein each clock cycle corresponds to one pixel data transmission;

a counter for counting the number pixel data transmissions; and

a register programmed with a maximum value, wherein the maximum value is greater than or equal to the number of clock cycles needed to transmit pixel data from all pixels in the pixel array.

3. The system of claim 1 , wherein the error condition comprises at least one of a pixel data read out error, a pixel data retrieval error, and a pixel data storage error.

4. A method for detecting errors in an imaging system, comprising: generating a frame of pixel data from a pixel array;

transmitting the frame of pixel data to an error detection circuit; performing error analysis on the frame of pixel data with the error detection circuit using count values corresponding to individual pixel data transmission per frame;

generating an error signal with the error detection circuit to indicate an error condition;

operating an image signal processor according to the error signal, where the image signal processor indicates a process to capture and receive new pixel data in response to the error signal; and

preventing use of the second pixel data in response to the error signal,

wherein performing error analysis with the error detection circuit comprises:

receiving a predetermined value. wherein the predetermined value is greater than the number of pixels in the pixel array;

receiving a clock signal that corresponds to a single pixel data transmission;

counting down from the predetermined value according to the clock signal; and

generating N bits that represent the count value.

5. The method of claim 4 , wherein performing error analysis with the error detection circuit comprises:

transmitting the pixel data to an image processing unit on a one pixel per clock cycle basis;

counting the number of clock cycles needed to transmit the pixel data; and

comparing the number of clock cycles to a maximum value.

6. The method of claim 5 , wherein the error signal is generated if the number of clock cycles is greater than the maximum value.

7. An apparatus for error detection, comprising: an imaging system comprising:

a pixel array comprising a plurality of pixels configured to capture an image and generate an image frame comprising a frame of pixel data;

an error detection circuit coupled to the pixel array and configured to: receive the frame of pixel data;

measure a readout time for the frame of pixel data based on a count value corresponding to individual pixel data transmissions per frame; and

generate an error signal based on the measured readout time; and

an embedded system coupled to the imaging system and responsive to the error signal;

wherein the error signal prevents the embedded system from using the frame of pixel data,

wherein the error detection circuit comprises: a register configured to store a predetermined value,

wherein the predetermined value is greater than the number of pixels in the pixel array; and

an N-bit counter connected to the register and configured to receive the predetermined value and generate N bits that represent the count value.

8. The apparatus of claim 7 , wherein the error detection circuit comprises:

a clock for generating clock cycles, wherein each clock cycle corresponds to one pixel data transmission;

a counter for counting the number of clock cycles; and

a register programmed with a maximum value, wherein the maximum value is greater than or equal to the number of clock cycles needed to transmit pixel data from all pixels in the pixel array.

9. The apparatus of claim 7 , wherein the error signal corresponds to at least one of a pixel data read out error, a pixel data retrieval error, and a pixel data storage error.

10. The system of claim 1 , wherein the N-bit counter comprises a first input terminal and a second input terminal, and is configured to:

receive a sync signal at the first input terminal and begin counting in response to the sync signal; and

receive a clock signal at the second input terminal and generate the N-bit count value according to the clock signal, wherein the clock signal corresponds to a single data transmission.

11. The system of claim 10 , wherein the N-bit counter counts down from the predetermined value according to the clock signal.

12. The method of claim 4 , wherein performing error analysis with the error detection circuit further comprises:

receiving a sync signal;

beginning counting in response to the sync signal; and generating a signal output signal according to the N bits.

13. The apparatus of claim 7 , wherein the N-bit counter comprises a first input terminal and a second input terminal, and is configured to:

receive a sync signal at the first input terminal and begin counting in response to the sync signal; and

receive a clock signal at the second input terminal and generate the N-bit count value according to the clock signal, wherein the clock signal corresponds to a single pixel data transmission.

14. The apparatus of claim 13 , wherein the N-bit counter counts down from the predetermined value according to the clock signal.