PowerMOS
A process of manufacturing a device is disclosed. The process includes forming an epitaxial layer of a first conductivity type on in a substrate, forming a first vertical section of a second conductivity type in the expitaxial layer, creating a first vertical trench through etching vertically next to the first vertical section, filling the first vertical trench with a first type oxide, forming a second vertical trench in the first vertical trench. The second vertical trench is bounded by the first type oxide in the first vertical trench. The process further includes forming a second type oxide on inner walls of the second vertical trench, filling the second vertical trench with polysilicon. In a second vertical section of the epitaxial layer vertically next to the first vertical trench, a body region is created by implanting ions of the first conductivity type and a source region is created by implanting ions in a top layer of the body region.
1. A process of manufacturing a device, the process comprising:
forming an epitaxial layer of a first conductivity type on in a substrate;
forming a first vertical section of a second conductivity type in the expitaxial layer;
creating a first vertical trench through etching vertically next to the first vertical section;
filling the first vertical trench with a first type oxide;
forming a second vertical trench in the first vertical trench, wherein the second vertical trench is bounded by the first type oxide in the first vertical trench;
forming a second type oxide on inner walls of the second vertical trench;
filling the second vertical trench with polysilicon;
in a second vertical section of the epitaxial layer vertically next to the first vertical trench, implanting ions of the first conductivity type to create a body region; and
in the second vertical section, implanting ions to create a source region in a top layer of the body region.
2. The process of manufacturing of claim 1 , further including forming a layer of the first type oxide over the first vertical section, the first vertical trench and the second vertical section.
3. The process of manufacturing of claim 1 , wherein the first type oxide is tetraethylorthosilicate (TEOS dielectric).
4. The process of manufacturing of claim 1 , wherein the second type oxide is silicon dioxide.
5. The process of manufacturing of claim 1 , wherein the first conductivity type is n-type.
6. The process of manufacturing of claim 1 , wherein the second conductivity type is p-type.
7. The device of claim 1 , wherein the source region is formed over the body region such that the source region fully covers the body region.
8. The device of claim 1 , wherein each of the two symmetrical and identical cells includes a dielectric layer that substantially covers the gate electrode and the source region.
9. A device, comprising:
a substrate having an epitaxial layer of a first conductivity type;
two symmetrical and identical cells embodied in the epitaxial layer, wherein each of the two symmetrical cells includes a deep trench, a Reduced Surface Field (RESURF) plate of a second conductivity type, a gate electrode embodied in the deep trench, a body region, a source region, and a drain region; and
wherein the two symmetrical cells are combined such that the combination shares the drain region and the RESURF plate, and the RESURF plate is between vertical sidewalls from each deep trench of the two symmetrical cells.
10. The device of claim 9 , wherein the deep trench is filled with an oxide.
11. The device of claim 9 , wherein the body region is of the second conductivity type.
12. The device of claim 9 , wherein the gate electrode in embodied in the deep trench.
13. The device of claim 12 , wherein the gate electrode is filled with polysilicon and bound by a gate oxide.