IP Library Granted Patent US 10,461,090
Granted Patent B2
US 10,461,090 · App. 15/263,827 · Granted Oct 29, 2019

Semiconductor memory device and method of manufacturing the same

Inventor: Ming Hu (Yokkaichi, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L27/11565H01L27/1157H01L27/11575H01L27/11582
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Quick Facts
Patent No.
US 10,461,090
App. No.
15/263,827
Granted
Oct 29, 2019
Kind
B2
Abstract

A semiconductor memory device according to an embodiment comprises a substrate, a plurality of first conductive films, a memory columnar body, and a first structure. The plurality of first conductive films are stacked in a first direction above the substrate and extend in a second direction intersecting the first direction and in a third direction intersecting the first direction and the second direction. The memory columnar body extends in the first direction and has a side surface covered by the plurality of first conductive films. The first structure extends in the second direction and divides the plurality of first conductive films in the third direction. Moreover, each of the memory columnar body and the first structure comprises: a memory insulating film provided on a side surface of the first conductive film; and a first semiconductor layer provided on a side surface of the memory insulating film.

Claims (43)

1. A semiconductor memory device, comprising:

a substrate;

a plurality of first conductive films stacked in a first direction above the substrate and extend in a second direction intersecting the first direction and in a third direction intersecting the first direction and the second direction;

a memory columnar body extending in the first direction and having a side surface covered by the plurality of first conductive films; and

a first structure extending in the second direction and dividing the plurality of first conductive films in the third direction, a length of the first structure in the second direction being greater than a length of the first structure in the third direction, and the length of the first structure in the second direction being equal to or greater than a length of the plurality of first conductive films in the second direction,

each of the memory columnar body and the first structure comprising:

a memory insulating film provided on a side surface of at least one of the plurality of first conductive films; and

a first semiconductor layer provided on a side surface of the memory insulating film.

2. The semiconductor memory device according to claim 1 , wherein

the memory insulating film comprises a first insulating film, a charge accumulation film, and a second insulating film provided sequentially on the side surface of a first conductive film of the plurality of first conductive films.

3. The semiconductor memory device according to claim 1 , comprising:

a memory plane provided above the substrate and including the plurality of first conductive films and the memory columnar body; and

a plurality of the first structures arranged at first intervals in the third direction,

wherein the memory plane is divided into a plurality of sub-planes by the plurality of first structures.

4. The semiconductor memory device according to claim 3 , further comprising

a plurality of second structures arranged in the third direction at second intervals smaller than the first intervals, extending in the second direction, and dividing the plurality of first conductive films in the third direction,

wherein the memory plane is divided into a plurality of memory fingers by the plurality of second structures, and

a sub-plane of the plurality of sub-planes includes a plurality of the memory fingers.

5. The semiconductor memory device according to claim 4 , further comprising:

a second semiconductor layer connected to a lower end of the memory columnar body and extending in the third direction;

a source line contact connected at a lower end thereof to the second semiconductor layer and extending in the first direction; and

a source line provided above the source line contact and connected to the source line contact,

wherein the second structure includes the source line contact.

6. The semiconductor memory device according to claim 4 , wherein

the memory plane comprises:

a first memory finger provided within the sub-plane; and

a second memory finger provided at a boundary of two of the sub-planes adjacent in the third direction,

the first memory finger is a memory finger recording user data, and

the second memory finger is a dummy finger not recording user data.

7. The semiconductor memory device according to claim 6 , wherein

the memory plane further comprises a third memory finger provided between the first memory finger and the second memory finger, and

the third memory finger is a dummy finger not recording user data.

8. The semiconductor memory device according to claim 1 , wherein

each of the memory columnar body and the first structure further comprises a third insulating film having a side surface covered by the first semiconductor layer.

9. The semiconductor memory device according to claim 1 , wherein

the first semiconductor layer extends in the first direction, and

each of the memory columnar body and the first structure further comprises a third semiconductor layer provided at a lower end of the first semiconductor layer.

10. The semiconductor memory device according to claim 1 , wherein

the length of the first structure in the third direction is greater than a length of the memory columnar body in the third direction.

11. The semiconductor memory device according to claim 1 , wherein

the first structure has a substantially rectangular shape when viewed from the first direction.

12. The semiconductor memory device according to claim 1 , wherein

the first structure includes at least one slit that extends along the length of the plurality of first conductive films in the second direction and creates a space between the divided plurality of first conductive films in the third direction so as to suppress thermal contraction of the semiconductor memory device in the third direction.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043541/0381 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2016
From: HU, MING
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 039718/0662 →
Continuity (2)
Provisional Application 62365431 · Jul 22, 2016
Related Publication 20180026045A1 · Jan 25, 2018