IP Library Granted Patent US 9,865,612
Granted Patent B2
US 9,865,612 · App. 15/263,832 · Granted Jan 9, 2018

Semiconductor memory device and method of manufacturing the same

Inventor: Shinya Arai (Yokkaichi, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L27/11568G11C16/0466G11C16/26H01L21/28282H01L27/11551H01L27/11553
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Quick Facts
Patent No.
US 9,865,612
App. No.
15/263,832
Granted
Jan 9, 2018
Kind
B2
Abstract

A semiconductr memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body. The columnar semiconductor layer has a boundary of the first portion and the second portion, the boundary being close to the second insulating layer; and an average value of an outer diameter of the memory layer facing a side surface of the second insulating layer is larger than that of of the memory layer facing a side surface of a lowermost layer of the first insulating layers in the second portion.

Claims (42)

1. A semiconductor memory device, comprising:

a semiconductor substrate;

a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate;

a columnar semiconductor layer being provided above the semiconductor substrate in the stacked body, being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion;

a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and

a second insulating layer provided between one of the first insulating layers of the stacked body and the conductive layer,

the columnar semiconductor layer having a boundary of the first portion and the second portion, the boundary being close to the second insulating layer,

an average value of an outer diameter of the memory layer facing a side surface of the second insulating layer being larger than that of the memory layer facing a side surface of a lowermost layer of the first insulating layers in the second portion, and

a diameter of an inner sidewall of the second insulating layer facing a side surface of the memory layer increasing downwardly.

2. The semiconductor memory device according to claim 1 , wherein

a central axis passing through a center of a cross section parallel to a surface of the substrate, of the first portion, and a central axis passing through a center of a cross section parallel to the surface of the substrate, of the second portion are in different positions in a direction parallel to the surface of the substrate.

3. The semiconductor memory device according to claim 1 , wherein

the first insulating layer includes silicon and oxygen, and

the second insulating layer includes silicon and oxygen, and has an etching rate with respect to a hydrofluoric acid solution higher than that of the first insulating layer.

4. The semiconductor memory device according to claim 1 , wherein

a film thickness of the second insulating layer is substantially identical to that of the first insulating layer.

5. The semiconductor memory device according to claim 1 , wherein

a total of a film thickness of the first insulating layer and a film thickness of the second insulating layer is 70 nm or less.

6. The semiconductor memory device according to claim 1 , wherein

the diameter of the second insulating layer is a diameter in the direction orthogonal to the stacking direction of the stacked body.

7. A method of manufacturing a semiconductor memory device, comprising:

alternately stacking a plurality of first insulating layers and first layers on a semiconductor substrate, thereby forming a first stacked body;

forming a first hole penetrating the plurality of first insulating layers and the plurality of first layers;

forming a first sacrifice layer in the first hole;

forming a second insulating layer on the first stacked body, and alternately stacking a plurality of the first insulating layers and the first layers on the second insulating layer, thereby forming a second stacked body;

forming a second hole penetrating the second stacked body and exposing an upper surface of the first sacrifice layer;

removing the first sacrifice layer and an inner sidewall of the second insulating layer by etching via the second hole, thereby forming a third hole; and

forming a memory film and a semiconductor layer on an inner wall of the third hole.

8. The method of manufacturing a semiconductor memory device according to claim 7 , wherein

the first sacrifice layer is formed using a material that includes silicon.

9. The method of manufacturing a semiconductor memory device according to claim 7 , further comprising

during the etching, employing a method of a kind where an etching rate of the second insulating layer will be higher than that of the first insulating layer.

10. The method of manufacturing a semiconductor memory device according to claim 7 , wherein

the first insulating layer and second insulating layer are silicon oxide layers formed using a plasma CVD (Chemical Vapor Deposition) method.

11. The method of manufacturing a semiconductor memory device according to claim 10 , wherein

the plasma CVD forming the second insulating layer is performed under an atmosphere of 200° C. or less.

12. The method of manufacturing a semiconductor memory device according to claim 10 , wherein

the etching is wet etching employing a dilute hydrofluoric acid solution.

13. The method of manufacturing a semiconductor memory device according to claim 7 , wherein

the inner sidewall of the second insulating layer is removed to increase an inner diameter of the second insulating layer downwardly.

14. The method of manufacturing a semiconductor memory device according to claim 13 , wherein

the inner diameter of the second insulating layer is a diameter in a direction orthogonal to a stacking direction of the first and second stacked body.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043541/0381 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2016
From: ARAI, SHINYA
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 039718/0664 →
Continuity (2)
Provisional Application 62311546 · Mar 22, 2016
Related Publication 20170278857A1 · Sep 28, 2017