Memory device and operating method including a partial program operation and a partial erase operation thereof
There are provided a memory device and an operating method thereof. A memory device may include a memory block, peripheral circuits, and a control logic. The memory block may include a plurality of pages arranged in a vertical direction on a substrate. The peripheral circuits may perform a program operation on a selected page. The control logic may control the peripheral circuits to perform a first partial program operation of sequentially programming some of the pages up to a first page. The control logic may perform a first partial erase operation of erasing the other non-programmed pages. The control logic may perform a second partial program operation of partially programming the pages on which the first partial erase operation has been performed.
1. A method of operating a memory device, the method comprising:
programming memory cells of first and second strings vertically arranged on a substrate, the first and second strings being coupled to each other through lower portions thereof, a first memory cell located at an uppermost end of the first string being programmed first, and then a second memory cell located at an uppermost end of the second string being programmed after the first memory cell is programmed;
programming a third memory cell located at a lower position than the first memory cell after the second memory cell is programmed and then programming a fourth memory cell located at a lower position than the second memory cell after the third memory cell is programmed;
programming an N th memory cell of the first string after the fourth memory cell is programmed, programming an (N+1) th memory cell of the second string after the N th memory cell is programmed, and then erasing memory cells located at lower positions than the N th and (N+1) th memory cells; and programming the erased memory cells.
2. The method of claim 1 , wherein programming the memory cells located at the lower positions of the N th and (N+1) th memory cells includes programming all of the memory cells located at the lower positions of the N th and (N+1) th memory cells, or sequentially programming some of the memory cells located at the lower positions of the N th and (N+1) th memory cells and then erasing and programming the other non-programmed memory cells.
3. A memory device comprising:
a memory block including first and second strings vertically arranged on a substrate, wherein lower portions of the first and second strings are coupled to each other, an upper portion of the first string is coupled to a bit line, and an upper portion of the second string is coupled to a source line;
peripheral circuits configured to perform a program operation on a selected page included in the first or second string; and
a control logic configured to control the peripheral circuits to program a first memory cell located at an uppermost end of the first string, and program a second memory cell located at an uppermost end of the second string after the first memory cell is programmed, program a third memory cell located at a lower position than the first memory cell after the second memory cell is programmed, program a fourth memory cell located at a lower position than the second memory cell after the third memory cell is programmed, erase unprogrammed memory cells of the first and second strings if a set page is programmed, and program the unprogrammed memory cells after the unprogrammed memory cells are erased.
4. The memory device of claim 3 , wherein the control logic controls the peripheral circuits to erase the unprogrammed memory cells located under the set page.
5. The memory device of claim 3 , wherein the control logic controls the peripheral circuits to erase the unprogrammed memory cells simultaneously.