SYSTEMS AND METHODS FOR DYNAMICALLY ASSIGNING DOMAIN IDENTIFIERS FOR ACCESS CONTROL
A master domain assignment controller includes a first plurality of registers corresponding to a first processor including a first register corresponding to a first set of process identifiers (PIDs) and a second register corresponding to a second set of PIDs, and comparison circuitry. The comparison circuitry is coupled to receive an input PID from the first processor and is configured to determine if the input PID is one of the first set or the second set of PIDs. When the input PID is one of the first set of PIDs, a first output domain identifier (DID) is generated, and when the input PID is one of the second set of PIDs, a second output DID different from the first output DID is generated.
1 . A master domain assignment controller (MDAC) comprising:
a first plurality of registers corresponding to a first processor, the first plurality of registers comprising a first register corresponding to a first set of process identifiers (PIDs) and a second register corresponding to a second set of PIDs; and
comparison circuitry coupled to receive an input process identifier (PID) from the first processor and configured to determine if the input PID is one of the first set or the second set of PIDs, wherein:
when the input PID is one of the first set of PIDs, a first output domain identifier (DID) is generated, and
when the input PID is one of the second set of PIDs, a second output DID different from the first output DID is generated.
2 . The MDAC of claim 1 , wherein the first register is configured to store a first group identifier which identifies the first set of PIDs and the second register is configured to store a second group identifier which identifies the second set of PIDs, wherein the comparison circuitry is configured to use the first group identifier to determine if the input PID is one of the first set of PIDs and the second group identifier to determine if the input PID is one of the second set of PIDs.
3 . The MDAC of claim 2 , wherein the first group identifier includes a first PID and a first PID mask, and the second group identifier includes a second PID and a second PID mask, wherein the comparison circuitry is configured to use the first PID masked by the first PID mask to determine if the input PID is one of the first set of PIDs and the second PID masked by the second PID mask to determine if the input PID is one of the second set of PIDs.
4 . The MDAC of claim 3 , wherein the first group identifier includes a first PID enable indicator, wherein the comparison circuitry is configured to:
when the first PID enable indicator has a first value, the input PID is one of the first set of PIDs if the first PID masked by the first PID mask matches the input PID masked by the first PID mask, and
when the first PID enable indicator has a second value, the input PID is one of the first set of PIDs if the first PID masked by the first PID mask does not match the input PID masked by the first PID mask.
5 . The MDAC of claim 4 , wherein the second group identifier is configured to store a second PID enable indicator, wherein the comparison circuitry is configured to:
when the second PID enable indicator has the first value, the input PID is one of the second set of PIDs if the second PID masked by the second PID mask matches the input PID masked by the second PID mask, and
when the second PID enable indicator has the second value, the input PID is one of the second set of PIDs if the second PID masked by the second PID mask does not match the input PID masked by the second PID mask.
6 . The MDAC of claim 2 , wherein the first register is configured to store a first DID and the second register is configured to store a second DID, wherein:
when the input PID is one of the first set of PIDs, the first output DID is generated using the first DID, and
when the input PID is one of the second set of PIDs, the second output DID is generated using the second DID.
7 . The MDAC of claim 2 , wherein the first register is configured to store a first DID and a first DID select and the second register is configured to store a second DID and a second DID select, wherein:
when the input PID is one of the first set of PIDs, the first output DID is generated using the first DID select and at least one of the first DID and an input DID received from the processor, and
when the input PID is one of the second set of PIDs, the second output DID is generated using the second DID select and at least one of the second DID and the input DID.
8 . The MDAC of claim 7 , wherein:
when the input PID is one of the first set of PIDs and the first DID select has a first value, the first DID is provided as the first output domain identifier, and
when the input PID is one of the first set of PIDs and the first DID select has a second value, an input DID received from the processor is provided as the first output DID.
9 . The MDAC of claim 8 , wherein when the input PID is one of the first set of PIDs and the first DID select has a third value, a combination of the first DID and an input DID received from the processor is provided as the first output DID.
10 . The MDAC of claim 1 , further comprising:
a plurality of MDAC instances, wherein each MDAC instance comprises:
one or more registers corresponding to a corresponding master coupled to the MDAC, and
corresponding comparison circuitry configured to generate a corresponding output DID using the one or more registers in response to a corresponding input PID,
wherein the one or more registers of a first MDAC instance of the plurality of MDAC instances correspond to the first and second registers.
11 . A resource domain controller comprising:
a master domain assignment controller (MDAC) ( 104 ) having a plurality of MDAC instances, wherein each MDAC instance corresponds to a corresponding master ( 102 ) coupled to the MDAC and a first MDAC instance of the plurality of MDAC instances corresponding to a first master includes:
a plurality of registers (e.g. 202 ), wherein each register is configured to store a group identifier (e.g. PID, PIDM, and PE) which identifies a set of PIDs, and
comparison circuitry configured to generate a first output DID using a hit register of the plurality of registers whose group identifier results in a hit of a first input PID received from the first master, wherein the first input PID is one of the set of PIDs identified by the group identifier of the hit register; and
a switch fabric ( 106 ) coupled to receive the first output DID from the MDAC and coupled to a plurality of slaves, wherein the switch fabric is configured to provide communication between the masters and the slaves.
12 . The resource domain controller of claim 11 , wherein the first master provides the first input PID and an input DID to the MDAC, and an address and address attributes to the switch fabric, and the MDAC provides the first output DID to the switch fabric.
13 . The resource domain controller of claim 11 , wherein each group identifier of the first MDAC instance includes a PID and a PID mask, wherein the comparison circuitry determines which register of the plurality of registers results in a hit using the PIDs and PID masks.
14 . The resource domain controller of claim 13 , wherein each group identifier of the first MDAC instance includes a PID enable indicator, wherein the comparison circuitry determines which register of the plurality of registers results in a hit using the PIDs, the PID masks, and the PID enable indicators, wherein:
if the PID enable indicator stored in the hit register has a first value, the PID stored in the hit register masked by the PID mask stored in the hit register matches the first input PID masked by the PID mask stored in the hit register, and
if the PID enable indicator stored in the hit register has a second value, the PID stored in the hit register masked by the PID mask stored in the hit register does not match the first input PID masked by the PID mask stored in the hit register.
15 . The resource domain controller of claim 11 , each register of the plurality of registers of the first MDAC instance is configured to store a DID and a DID select, wherein the first output DID is generated using the DID select stored in the hit register and at least one of the DID stored in the hit register and an input DID received from the processor.
16 . In a master domain assignment controller (MDAC) having a plurality of registers, wherein each register is configured to store a group identifier which identifies a set of process identifiers (PIDs), a method comprises:
receiving an input PID;
determining if a hit occurs with a register of the plurality of registers using the group identifier of each register; and
when a hit is determined of a hit register of the plurality of registers which indicates that the input PID is one of the set of PIDs identified by the hit register, generating an output DID using the hit register.
17 . The method of claim 16 , wherein the group identifier of each register includes a corresponding PID and PID mask, wherein the determining if the hit occurs with the register of the plurality of registers using the group identifier of each register is performed by using the PID and PID mask of each register.
18 . The method of claim 17 , wherein the group identifier of each register includes a corresponding PID enable indicator, wherein the determining if the hit occurs with the register of the plurality of registers further comprises:
when the corresponding PID enable indicator has a first value and the corresponding PID masked by the corresponding PID mask matches the input PID masked by the corresponding PID mask, a hit is determined; and
when the corresponding PID enable indicator has a second value and the corresponding PID masked by the corresponding PID mask does not match the input PID masked by the corresponding PID mask, a hit is determined.
19 . The method of claim 18 , wherein each register of the plurality of registers is configured to store a corresponding DID and a corresponding DID select, the method further comprising:
receiving an input DID, wherein the generating the output DID using the hit register comprises:
when the corresponding DID select of the hit register has a first value, the corresponding DID of the hit register is provided as the output DID; and
when the corresponding DID select of the hit register has a second value, the input DID is provided as the output DID.
20 . The method of claim 16 , wherein each register of the plurality of registers is configured to store a corresponding DID, the method further comprising:
when a hit is determined of multiple hit registers of the plurality of registers in which each register of the multiple hit registers indicates that the input PID is one of the set of PIDs identified by the register of the multiple hit registers, generating an output DID using the corresponding DID of each of the multiple hit registers.