IP Library Granted Patent US 10,411,162
Granted Patent B2
US 10,411,162 · App. 15/265,069 · Granted Sep 10, 2019

Semiconductor light-emitting device including penetrating trenches

Inventors: Chao-Hsing Chen (Hsinchu, TW); Jia-Kuen Wang (Hsinchu, TW); Tzu-Yao Tseng (Hsinchu, TW); Tsung-Hsun Chiang (Hsinchu, TW); Bo-Jiun Hu (Hsinchu, TW); Wen-Hung Chuang (Hsinchu, TW); Yu-Ling Lin (Hsinchu, TW)
Assignee: EPISTAR CORPORATION
H01L33/382H01L33/387H01L33/46H01L33/62H01L33/0012H01L33/08H01L33/22H01L33/38H01L2224/48091H01L2224/73265
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Quick Facts
Patent No.
US 10,411,162
App. No.
15/265,069
Granted
Sep 10, 2019
Kind
B2
Abstract

A semiconductor light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer; a plurality of first trenches penetrating the second semiconductor layer and the active layer to expose the first semiconductor layer; a second trench penetrating the second semiconductor layer and the active layer to expose the first semiconductor layer, wherein the second trench is disposed near an outmost edge of the active layer, and surrounds the active layer and the plurality of first trenches; a patterned metal layer formed on the second semiconductor layer and formed in one of the plurality of first trenches or the second trench; and a first pad portion and a second pad portion both formed on the second semiconductor layer and electrically connecting the second semiconductor layer and the first semiconductor layer respectively.

Claims (42)

1. A semiconductor light-emitting device, comprising:

a substrate;

a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer formed on the substrate;

a plurality of semiconductor constructions formed on the substrate, respectively comprising the first semiconductor layer, the second semiconductor layer, and the active layer;

a plurality of first trenches penetrating the second semiconductor :layer and the active layer to expose the first semiconductor layer;

a second trench penetrating the second semiconductor layer and the active layer to expose a periphery region of the first semiconductor layer, wherein the second trench is disposed near an outmost edge of the active layer, and surrounds the plurality of semiconductor constructions and the plurality of first trenches, wherein the first semiconductor layer of each of the plurality of semiconductor constructions are connected to each other through the first semiconductor layer exposed by the plurality of first trenches and the second trench in a cross-sectional view of the semiconductor light-emitting device, and the second semiconductor layer of each of the plurality of semiconductor constructions are separated from each other by one of the plurality of first trenches in a top view of the semiconductor light-emitting device;

a patterned metal layer formed on the plurality of semiconductor constructions and filling in the plurality of first trenches and the second trench;

a plurality of first pad portions physically separated from each other, respectively formed on the second semiconductor layer of each of the plurality of semiconductor constructions; and

a plurality of second pad portions physically separated from each other, respectively formed on the second semiconductor layer of each of the plurality of semiconductor constructions,

wherein the periphery region of first semiconductor layer comprises a top surface exposed by the second trench and a periphery side surface connecting to the top surface of the first semiconductor layer of the periphery region,

wherein the periphery side surface is an exposed outermost side surface of the first semiconductor layer of the periphery region, and

wherein the patterned metal layer comprises a plurality of first metal regions physically separated from each other, respectively formed on the second semiconductor layer of each of the plurality of semiconductor constructions, and a second metal region electrically isolated to the plurality of first metal regions, and portions of the second metal region are formed in the plurality of first trenches and the second trench.

2. The semiconductor light-emitting device of claim 1 , wherein a width of one of the plurality of first trenches is greater than a width of the second trench.

3. The semiconductor light-emitting device of claim 1 , wherein the plurality of first pad portions is aligned with the plurality of second pad portions.

4. The semiconductor light-emitting device of claim 1 , wherein in a top view, a shape composed by the plurality of first trenches and the second trench comprises a plurality of rectangles, and the plurality of first pad portions and the plurality of second pad portions are respectively disposed in the plurality of rectangles.

5. The semiconductor light-emitting device of claim 1 , wherein the plurality of first trenches is parallel to one another in the top view of the semiconductor light-emitting device.

6. The semiconductor light-emitting device of claim 1 , further comprising a transparent conductive layer formed on the second semiconductor layers of each of the plurality of semiconductor constructions.

7. The semiconductor light-emitting device of claim 6 , wherein the transparent conductive layer comprises indium tin oxide (ITO) or indium zinc oxide (IZO).

8. The semiconductor light-emitting device of claim 6 , further comprising a reflective layer formed on the transparent conductive layer of the plurality of semiconductor constructions.

9. The semiconductor light-emitting device of claim 1 , further comprising a reflective layer formed on the second semiconductor layers of the plurality of semiconductor constructions.

10. The semiconductor light-emitting device of claim 9 , further comprising a second insulating layer covers the plurality of semiconductor constructions, wherein the second insulating layer comprises a plurality of second insulating openings respectively exposing the reflective layer of the plurality of semiconductor constructions.

11. The semiconductor light-emitting device of claim 10 , wherein the second insulating layer comprises a distributed Bragg reflector (DBR) which includes a plurality pairs of sub-layers, and each sub-layer has a refractive index different from that of adjacent sub-layers.

12. The semiconductor light-emitting device of claim 1 , further comprising a first insulating layer covering the periphery side surface.

13. The semiconductor light-emitting device of claim 1 , wherein the plurality of first trenches are connected to the second trench in the top view of the semiconductor light-emitting device.

14. A semiconductor light-emitting device, comprising:

a substrate;

a first semiconductor layer formed on the substrate;

a plurality of semiconductor constructions formed on the substrate, respectively comprising the first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer;

a plurality of first trenches exposing the first semiconductor layer;

a second trench exposing a periphery region of the first semiconductor layer, wherein the second trench is disposed near an outmost edge of the active layer, and surrounds the plurality of semiconductor constructions and the plurality of first trenches, wherein the first semiconductor layer of each of the plurality of semiconductor constructions are connected to each other through the first semiconductor layer exposed by the plurality of first trenches and the second trench in a cross-sectional view of the semiconductor light-emitting device, and the second semiconductor layer of each of the plurality of semiconductor constructions are separated from each other in a top view of the semiconductor light-emitting device;

a patterned metal layer formed on the plurality of semiconductor constructions and filling in the plurality of first trenches and the second trench;

a plurality of first pad portions respectively formed on the second semiconductor layer of each of the plurality of semiconductor constructions;

a plurality of second pad portions respectively formed on the second semiconductor layer of each of the plurality of semiconductor constructions,

wherein the periphery region of first semiconductor layer comprises a top surface exposed by the second trench and a periphery side surface connecting to the top surface of the first semiconductor layer of the periphery region,

wherein the periphery side surface is an exposed outermost side surface of the first semiconductor layer of the periphery region, and

wherein the patterned metal layer comprises a plurality of first metal regions respectively formed on the second semiconductor layers of the plurality of semiconductor constructions, and a second metal region electrically isolated to the plurality of first metal regions, and portions of the second metal region are formed in the plurality of first trenches and the second trench; and

a third insulating layer covering the plurality of semiconductor constructions, wherein the third insulating layer comprises a first group of third insulating openings respectively exposing the plurality of first metal regions, and a second group of third insulating openings respectively exposing the second metal region of the plurality of semiconductor constructions.

15. The semiconductor light-emitting device of claim 14 , wherein the plurality of first pad portions is aligned with the plurality of second pad portions.

16. The semiconductor light-emitting device of claim 14 , further comprising a transparent conductive layer formed on the second semiconductor layers of each of the plurality of semiconductor constructions.

17. The semiconductor light-emitting device of claim 14 , further comprising a reflective layer formed on the second semiconductor layers of the plurality of semiconductor constructions.

18. The semiconductor light-emitting device of claim 17 , further comprising a second insulating layer covering the plurality of semiconductor constructions, wherein the second insulating layer comprises a plurality of second insulating openings respectively exposing the reflective layer of the plurality of semiconductor constructions.

19. The semiconductor light-emitting device of claim 14 , wherein the plurality of first trenches are connected to the second trench in the top view of the semiconductor light-emitting device.

Assignments (2)
CHANGE OF NAME Recorded Apr 22, 2026
From: EPISTAR CORPORATION
To: ENNOSTAR CORPORATION
Reel/Frame 075513/0783 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2016
From: CHEN, CHAO-HSING; WANG, JIA-KUEN; TSENG, TZU-YAO; CHIANG, TSUNG-HSUN; HU, BO-JIUN; CHUANG, WEN-HUNG; LIN, YU-LING
To: EPISTAR CORPORATION
Reel/Frame 040404/0719 →
Priority Claims (4)
TW 102130742 A · Aug 27, 2013 · national
TW 102143409 A · Nov 27, 2013 · national
TW 103119845 A · Jun 6, 2014 · national
TW 103124091 A · Jul 11, 2014 · national
Continuity (7)
Continuation 14853511 · Sep 14, 2015
Continuation In Part 14554488 · Nov 26, 2014
Continuation In Part 15265069
Continuation In Part 14948733 · Nov 23, 2015
Continuation In Part 14470396 · Aug 27, 2014
Provisional Application 62092422 · Dec 16, 2014
Related Publication 20170005232A1 · Jan 5, 2017