IP Library Granted Patent US 10,050,516
Granted Patent B2
US 10,050,516 · App. 15/266,005 · Granted Aug 14, 2018

Active clamp power converter and method of reducing shoot-through current during soft start

Inventors: Bryan Wayne McCoy (Chandler, AZ); Ajay Karthik Hari (Scottsdale, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H02M1/36H02M1/08H02M1/38H02M3/3353H02M3/33507H02M3/33569
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Quick Facts
Patent No.
US 10,050,516
App. No.
15/266,005
Granted
Aug 14, 2018
Kind
B2
Abstract

An ACF power converter uses a soft start operation to reduce overheating and stress on components. The power converter includes a first transistor and second transistor. A high side driver controls the first transistor, and low side driver controls the second transistor. A first operating potential is provided to the low side driver during a first period of time. The second transistor switches based on an oscillator signal having a first rate of frequency change to generate a second operating potential for the high side driver, while attempting to hold the first transistor in the non-conductive state during a second time period. The first and second transistors switch based on the oscillator signal having a second rate of frequency change during a third time period. The power converter is held in ACF mode and inhibited from changing state for a period of time post soft start.

Claims (32)

1. A method of controlling soft start in. a power converter including a first transistor and second transistor coupled in a conduction path with the first transistor, comprising:

switching the second transistor based on an oscillator signal having a first initial frequency while attempting to hold the first transistor in. the non-conductive state during a first time period; and

switching the first transistor and second transistor based on the oscillator signal having a second initial frequency during a second time period, wherein the oscillator signal has a first rate of frequency change during the first time period and a second rate of frequency change during the second time period.

2. The method of claim 1 , further including maintaining the first transistor and second. transistor in a non-conductive state during a third time period prior to the first time period.

3. The method of claim 1 , wherein the second rate of frequency change of the oscillator signal is less than the first rate of frequency change of the oscillator signal.

4. The method of claim 1 , further including:

providing a high side driver configured to control the first transistor;

providing a low side driver configured to control the second transistor; and

providing a first operating potential to the low side driver during the first period of time, wherein switching the second transistor during the first time period generates a second operating potential for the high side driver prior to the second time period.

5. The method of claim 4 , further including switching the second transistor based. on the oscillator signal having the first rate of frequency change while attempting to hold the first transistor in the non-conductive state during a fourth time period after the first time period to provide more time for the second operating potential to reach a threshold.

6. The method of claim 1 , wherein the first initial frequency during the first time period is 25 kHz.

7. A semiconductor device including a power converter with a soft start operation, comprising:

a power converter including a first transistor and second transistor coupled in a conduction path with the first transistor;

means for switching the second transistor based on an oscillator al having a first initial frequency while attempting to hold the first transistor in the non-conductive state during a first time period; and

means for switching the first transistor and second transistor based on the oscillator signal having a second initial frequency during a second time period, wherein the oscillator signal has a first rate of frequency change during the first time period and a second rate of frequency change during the second time period.

8. The semiconductor device of claim 7 , further including means for maintaining the first transistor and second transistor in a non-conductive state during a third time period prior to the first time period.

9. The semiconductor device of claim 7 , wherein the second rate of frequency change of the oscillator signal is less than the first rate of frequency change of the oscillator signal.

10. The semiconductor device of claim 7 , further including:

a high side driver configured to control the first transistor;

a low side driver configured to control the second transistor; and

means for providing a first operating potential to the low side driver during the first period of time, wherein switching the second transistor during the first time period generates a second operating potential for the high side driver prior to the second time period.

11. The semiconductor device of claim 10 , further including means for switching the second transistor based on the oscillator signal having the first rate of frequency change while attempting to hold the first transistor in the non-conductive state during a fourth time period after the first time period to provide more time for the second operating potential to reach a threshold.

12. The semiconductor device of claim 7 , wherein the first initial frequency during the first time period is 25 kHz.

13. A method of controlling soft start in a power converter including a first transistor and second transistor coupled in a conduction path with the first transistor, comprising:

switching the second transistor in response to an oscillator signal while holding the first transistor in the non-conductive state during a first time period;

changing a frequency of operation of the oscillator signal; and

switching the first transistor and second transistor in response to the oscillator signal during a second time period, wherein the oscillator signal has a first rate of frequency change during the first time period and a second rate of frequency change during the second time period.

14. The method of claim 13 , wherein the second rate of frequency change of the oscillator signal is less than the first rate of frequency change of the oscillator signal.

15. The method of claim 13 , further including:

providing a high side driver configured to control the first transistor;

providing a low side driver configured to control the second transistor; and

providing a first operating potential to the low side driver dl ring the first period of time, wherein switching the second transistor during the first time period generates a second operating potential for the high side driver prior to the second time period.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 041187, FRAME 0295 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064151/0203 →
SECURITY INTEREST Recorded Dec 23, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 041187/0295 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 15, 2016
From: MCCOY, BRYAN WAYNE; HARI, AJAY KARTHIK
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 039754/0150 →
Continuity (2)
Provisional Application 62314780 · Mar 29, 2016
Related Publication 20170288528A1 · Oct 5, 2017