Memory Control Circuit and Storage Device
A memory control circuit has a memory controller that performs access control for a first memory accessed by a first data amount and access control for a second memory of a memory layer equal to the first memory at a read speed lower than a read speed of the first memory by a second data amount larger than the first data amount.
1 . A memory control circuit comprising a memory controller that performs access control for a first memory accessed by a first data amount and access control for a second memory of a memory layer equal to the first memory at a read speed lower than a read speed of the first memory by a second data amount larger than the first data amount.
2 . The memory control circuit according to claim 1 , wherein the memory controller performs control of storing a part of data for which an access request is present in the first memory and performs control of storing the data for which the access request is present in the second memory.
3 . The memory control circuit according to claim 1 ,
wherein the first data amount is one word including a plurality of bits; and
wherein the second data amount is n times the word, where n is an integer of two or more.
4 . The memory control circuit according to claim 1 , wherein the memory controller comprises:
a first memory controller that performs access control for the first memory accessed by the first data amount;
a second memory controller that performs access control for the second memory by the second data amount; and
an access controller that controls an access to the first memory controller or the second memory controller.
5 . The memory control circuit according to claim 4 , wherein the access controller comprises data determining circuitry that determines data to be stored in the first memory.
6 . The memory control circuit according to claim 5 , wherein the memory controller, based on a determination performed by the data determining circuitry, after storing a part of data for which a write request is present in the first memory or while storing the data in the first memory, performs control of storing the data in the second memory.
7 . The memory control circuit according to claim 1 , wherein, in a case where a part of data for which a read request is present is stored in the first memory, the memory controller performs control of reading the part from the first memory and performs control of reading the data for which the read request is present from the second memory.
8 . The memory control circuit according to claim 7 , wherein, in a case where a part of the data for which the read request is present is not stored in the first memory, the memory controller performs control of reading the data from the second memory.
9 . The memory control circuit according to claim 1 , further comprising a buffer maintaining data stored or data to be stored in the second memory,
wherein the memory controller performs control of at least one of write control and read control for the first memory and the buffer based on an access request from the controller.
10 . The memory control circuit according to claim 9 ,
wherein the buffer is located inside the second memory, and
wherein the memory controller determines whether or not accessed data is maintained in the buffer and, in a case where the accessed data is maintained in the buffer, accesses the buffer located inside the second memory without accessing the first memory.
11 . The memory control circuit according to claim 1 , wherein data stored in the first memory includes word data to be transmitted first from a main memory.
12 . The memory control circuit according to claim 1 , wherein data stored in the first memory includes first word data of a page.
13 . The memory control circuit according to claim 1 , wherein data stored in the first memory includes first word data of data accessed in the past.
14 . The memory control circuit according to claim 1 , further comprising error detecting circuitry that performs error detection of data read from the first memory in the case of accessing the first memory,
wherein the memory controller sends the data read from the first memory to the controller in a case where an error is not detected by the error detecting circuitry and reads data for which a read request is present from the second memory and sends the read data to the controller in a case where an error is detected by the error detecting circuitry.
15 . The memory control circuit according to claim 1 , wherein a storable data capacity of the second memory is larger than a storable data capacity of the first memory.
16 . The memory control circuit according to claim 1 ,
wherein the first memory comprises a magnetoresistive RAM (MRAM), and
wherein the second memory comprises a dynamic RAM (DRAM).
17 . A storage device comprising:
a first memory accessed by a first data amount;
a second memory of a memory layer equal to the first memory at a read speed lower than a read speed of the first memory by a second data amount larger than the first data amount; and
a memory controller that performs access control for the first memory and the second memory.
18 . The storage device according to claim 17 , wherein the memory controller performs control of storing a part of data for which an access request is present in the first memory and performs control of storing the data for which the access request is present in the second memory.
19 . The storage device according to claim 17 , wherein the memory controller comprises:
a first memory controller that performs access control for the first memory accessed by the first data amount;
a second memory controller that performs access control for the second memory by the second data amount; and
an access controller that controls an access to the first memory controller or the second memory controller.
20 . The storage device according to claim 19 , wherein the access controller comprises data determining circuitry that determines data to be stored in the first memory.