Dynamic power reduction in circuit designs and circuits

1. A method of reducing dynamic power consumption for a circuit, the method comprising:

analyzing, using a processor, a netlist specifying the circuit to determine switching activity of a block of combinatorial circuitry in a first signal path;

comparing the switching activity of the block of combinatorial circuitry of the first signal path with a threshold amount of switching activity to determine whether the switching activity exceeds the threshold amount of switching activity;

detecting, using the processor, a second signal path coupled to the block of combinatorial circuitry by a sequential circuit element, the second signal path having a delay that meets a target signal path requirement; and

in response to determining that the switching activity exceeds the threshold amount of switching activity and the detecting the second signal path coupled to the block of combinatorial circuitry by the sequential circuit element, modifying, using the processor, the netlist by subdividing the block of combinatorial circuitry into at least a first portion and a second portion and moving one of the portions from the first signal path to the second signal path, wherein the moving separates the first portion from the second portion by the sequential circuit element;

wherein the portions of the block of combinatorial circuitry have an order prior to the modifying, and subsequent to the modifying, the portions of the block of combinatorial circuitry are separated only by one or more sequential circuit elements and the order of the portions is unchanged.

2. The method of claim 1 , wherein a configuration bitstream is generated from the modified netlist and loaded within a programmable integrated circuit to implement the modified netlist within the programmable integrated circuit.

3. The method of claim 1 , wherein the second signal path comprises combinatorial circuitry and the selected portion of the block of combinatorial circuitry abuts the combinatorial circuitry of the second signal path.

4. The method of claim 1 , wherein the first signal path meets a timing requirement.

5. The method of claim 1 , wherein a size of the selected portion is determined based upon a slack of the second signal path.

6. The method of claim 1 , wherein the block of combinatorial circuitry is subdivided into a number of portions determined based upon a number of target signal paths for the block of combinatorial circuitry.

7. The method of claim 1 , wherein the modified netlist is implemented within an integrated circuit.

8. A system for reducing dynamic power consumption of a circuit, comprising:

a processor configured to initiate executable operations including:

analyzing a netlist specifying the circuit to determine switching activity of a block of combinatorial circuitry in a first signal path;

comparing the switching activity of the block of combinatorial circuitry of the first signal path with a threshold amount of switching activity to determine whether the switching activity exceeds the threshold amount of switching activity;

detecting a second signal path coupled to the block of combinatorial circuitry by a sequential circuit element, the second signal path having a delay that meets a target signal path requirement; and

in response to determining that the switching activity exceeds the threshold amount of switching activity and the detecting the second signal path coupled to the block of combinatorial circuitry by the sequential circuit element, modifying the netlist by subdividing the block of combinatorial circuitry into at least a first portion and a second portion and moving one of the portions from the first signal path to the second signal path, wherein the moving separates the first portion from the second portion by the sequential circuit element;

wherein the portions of the block of combinatorial circuitry have an order prior to the modifying, and subsequent to the modifying, the portions of the block of combinatorial circuitry are separated only by one or more sequential circuit elements and the order of the portions is unchanged.

9. The system of claim 8 , wherein a configuration bitstream is generated from the modified netlist and implemented within a programmable integrated circuit to implement the modified netlist within the programmable integrated circuit.

10. The system of claim 8 , wherein the second signal path comprises combinatorial circuitry and the selected portion of the block of combinatorial circuitry abuts the combinatorial circuitry of the second signal path.

11. The system of claim 8 , wherein the first signal path meets a timing requirement.

12. The system of claim 8 , wherein a size of the selected portion is determined based upon a slack of the second signal path.

13. The system of claim 8 , wherein the block of combinatorial circuitry is subdivided into a number of portions determined based upon a number of target signal paths for the block of combinatorial circuitry.

14. The system of claim 8 , wherein the modified netlist is implemented within an integrated circuit.

15. A computer program product comprising a computer readable storage medium having program code stored thereon, the program code executable by a processor to perform a method of reducing dynamic power consumption for a circuit, the method comprising:

analyzing, using the processor, a netlist specifying the circuit to determine switching activity of a block of combinatorial circuitry in a first signal path;

comparing the switching activity of the block of combinatorial circuitry of the first signal path with a threshold amount of switching activity to determine whether the switching activity exceeds the threshold amount of switching activity;

detecting, using the processor, a second signal path coupled to the block of combinatorial circuitry by a sequential circuit element, the second signal path having a delay that meets a target signal path requirement; and

in response to determining that the switching activity exceeds the threshold amount of switching activity and the detecting the second signal path coupled to the block of combinatorial circuitry by the sequential circuit element, modifying, using the processor, the netlist by subdividing the block of combinatorial circuitry into at least a first portion and a second portion and moving one of the portions from the first signal path to the second signal path, wherein the moving separates the first portion from the second portion by the sequential circuit element;

wherein the portions of the block of combinatorial circuitry have an order prior to the modifying, and subsequent to the modifying, the portions of the block of combinatorial circuitry are separated only by one or more sequential circuit elements and the order of the portions is unchanged.

16. The computer program product of claim 15 , wherein a configuration bitstream is generated from the modified netlist and implemented within a programmable integrated circuit to implement the modified netlist within the programmable integrated circuit.

17. The computer program product of claim 15 , wherein the second signal path comprises combinatorial circuitry and the selected portion of the block of combinatorial circuitry abuts the combinatorial circuitry of the second signal path.

18. The computer program product of claim 15 , wherein a size of the selected portion is determined based upon a slack of the second signal path.

19. The computer program product of claim 15 , wherein the block of combinatorial circuitry is subdivided into a number of portions determined based upon a number of target signal paths for the block of combinatorial circuitry.

20. The computer program product of claim 15 , wherein the modified netlist is implemented within an integrated circuit.