Memory system and cache memory
A memory system has a non-volatile memory including a plurality of circuit blocks using different voltages, a power-off switch circuitry that switches whether or not voltage supply to each of the plurality of circuit blocks in the non-volatile memory is cut off, and a power-off controller that controls the switching of the power-off switch circuitry based on at least one of circuit volumes of the plurality of circuit blocks, standby power of the plurality of circuit blocks, and a circuit volume of the power-off switch circuitry.
1. A memory system, comprising:
a non-volatile memory including a plurality of circuit blocks using different voltages;
a power-off switch circuitry that switches whether or not voltage supply to each of the plurality of circuit blocks in the non-volatile memory is cut off; and
a power-off controller that controls the switching of the power-off switch circuitry based on operation frequencies of the plurality of circuit blocks and at least one of circuit volumes of the plurality of circuit blocks, standby power of the plurality of circuit blocks, or a circuit volume of the power-off switch circuitry,
wherein the non-volatile memory comprises a plurality of memory banks each of which comprises the plurality of circuit blocks,
the power-off switch circuitry switches whether or not the voltage supply to the plurality of circuit blocks in the memory bank is cut off for the memory bank, and
the power-off controller comprises a storage that holds access information for a memory bank in which the voltage supply is cut off.
2. The memory system according to claim 1 ,
wherein the power-off switch circuitry comprises a plurality of power-off switches of sizes depending on the circuit volumes of the circuit blocks for each memory bank.
3. The memory system according to claim 2 ,
wherein at least one of the plurality of power-off switches is a PMOS transistor whose substrate voltage is set to a predetermined voltage.
4. The memory system according to claim 1 ,
wherein the power-off controller cuts off voltage supply to a first circuit block having a first operation frequency before cutting off supply of a voltage to a second circuit block, the second circuit block having a second operation frequency higher than the first operation frequency.
5. The memory system according to claim 1 ,
wherein the non-volatile memory includes a magnetoresistive RAM (MRAM).
6. A memory system, comprising:
a non-volatile memory including a plurality of circuit blocks using different voltages;
a power-off switch circuitry that switches whether or not voltage supply to each of the plurality of circuit blocks in the non-volatile memory is cut off; and
a power-off controller that controls the switching of the power-off switch circuitry based on at least one of circuit volumes of the plurality of circuit blocks, standby power of the plurality of circuit blocks, and a circuit volume of the power-off switch circuitry,
wherein the power-off controller comprises:
a power-off order controller that controls a power-off order of the plurality of voltages using a predetermined state machine in which state transition is set based on parameters,
a parameters storage that stores the parameters, and
a parameters setting circuitry that sets the parameters in the power-off order controller.
7. A memory system, comprising:
a non-volatile memory including a plurality of circuit blocks using different voltages;
a power-off switch circuitry that switches whether or not voltage supply to each of the plurality of circuit blocks in the non-volatile memory is cut off; and
a power-off controller that controls the switching of the power-off switch circuitry based on at least one of circuit volumes of the plurality of circuit blocks, standby power of the plurality of circuit blocks, and a circuit volume of the power-off switch circuitry,
wherein the power-off controller cuts off supply of a voltage to a first circuit block having a first circuit volume before cutting off supply of a voltage to a second circuit block, the second circuit block having a second circuit volume larger than the first circuit volume.
8. A memory system, comprising:
a non-volatile memory including a plurality of circuit blocks using different voltages;
a power-off switch circuitry that switches whether or not voltage supply to each of the plurality of circuit blocks in the non-volatile memory is cut off; and
a power-off controller that controls the switching of the power-off switch circuitry based on at least one of circuit volumes of the plurality of circuit blocks, standby power of the plurality of circuit blocks, and a circuit volume of the power-off switch circuitry,
wherein the power-off controller cuts off voltage supply to a common ground of the plurality of circuit blocks, in a last order among the different voltages.
9. A cache memory, comprising:
a data cache that stores data and comprises a non-volatile memory comprising a plurality of circuit blocks using different voltages;
a tag that stores address information of the data stored in the data cache;
a power-off switch circuitry that switches whether or not voltage supply to each of the plurality of circuit blocks in the non-volatile memory is cut off; and
a power-off controller that controls the switching of the power-off switch circuitry based on at least one of circuit volumes of the plurality of circuit blocks, standby power of the plurality of circuit blocks, and a circuit volume of the power-off switch circuitry,
wherein the power-off controller cuts off supply of a voltage to a first circuit block having a first circuit volume before cutting off supply of a voltage to a second circuit block, the second circuit block having a second circuit volume larger than the first circuit volume.
10. A cache memory, comprising:
a data cache that stores data and comprises a non-volatile memory comprising a plurality of circuit blocks using different voltages;
a tag that stores address information of the data stored in the data cache;
a power-off switch circuitry that switches whether or not voltage supply to each of the plurality of circuit blocks in the non-volatile memory is cut off; and
a power-off controller that controls the switching of the power-off switch circuitry based on at least one of circuit volumes of the plurality of circuit blocks, standby power of the plurality of circuit blocks, and a circuit volume of the power-off switch circuitry,
wherein the power-off controller cuts off voltage supply to a common ground of the plurality of circuit blocks, in a last order among the different voltages.
11. A cache memory, comprising:
a data cache that stores data and comprises a non-volatile memory comprising a plurality of circuit blocks using different voltages;
a tag that stores address information of the data stored in the data cache;
a power-off switch circuitry that switches whether or not voltage supply to each of the plurality of circuit blocks in the non-volatile memory is cut off; and
a power-off controller that controls the switching of the power-off switch circuitry based on operation frequencies of the plurality of circuit blocks and at least one of circuit volumes of the plurality of circuit blocks, standby power of the plurality of circuit blocks, or a circuit volume of the power-off switch circuitry,
wherein the non-volatile memory comprises a plurality of memory banks each of which comprises the plurality of circuit blocks,
the power-off switch circuitry switches whether or not the voltage supply to the plurality of circuit blocks in the memory bank is cut off for the memory bank, and
the power-off controller comprises a storage that holds access information for a memory bank in which the voltage supply is cut off.
12. The cache memory according to claim 11 ,
wherein the memory bank stores data of a plurality of ways that are accessed in parallel.
13. The cache memory according to claim 11 ,
wherein the power-off switch circuitry comprises a plurality of power-off switches of sizes depending on the circuit volumes of the circuit blocks for each memory bank.
14. The cache memory according to claim 13 ,
wherein at least one of the plurality of power-off switches is a PMOS transistor whose substrate voltage is set to a predetermined voltage.
15. The cache memory according to claim 11 ,
wherein the power-off controller comprises:
a power-off order controller that controls a power-off order of the plurality of voltages using a predetermined state machine in which state transition is set based on parameters,
a parameters storage that stores the parameters, and
parameters setting circuitry that sets the parameters in the power-off order controller.
16. The cache memory according to claim 11 ,
wherein the non-volatile memory includes a magnetoresistive RAM (MRAM).