Laminar Phased Array Antenna
A phased array has a laminar substrate, a plurality of elements on the front side of the substrate, and a plurality of integrated circuits also on the front side of the substrate. This structure is arranged to form a patch phased array. The plurality of integrated circuits, which are configured to control receipt and/or transmission of signals by the plurality of elements in the phased array, preferably are wafer level chip scale packaging integrated circuits. Moreover, the plurality of integrated circuits are configured to operate at one or more satellite frequencies to have the capability of transmitting signals and/or receiving signals from a satellite.
1 . A phased array comprising:
a laminar substrate having a front side;
a plurality of elements on the front side of the laminar substrate forming a patch phased array;
a plurality of integrated circuits on the front side of the laminar substrate, the plurality of integrated circuits being wafer level chip scale packaging integrated circuits,
the plurality of integrated circuits configured to control receipt and/or transmission of signals by the plurality of elements in the patch phased array,
the plurality of integrated circuits configured to operate the phased array at one or more satellite frequencies to transmit signals to and/or receive signals from a satellite.
2 . The phased array as defined by claim 1 wherein the plurality of elements forms a triangular lattice.
3 . The phased array as defined by claim 1 wherein each integrated circuit is configured to control at least two elements.
4 . The phased array as defined by claim 1 wherein each integrated circuit includes a phase shifter to control the phase of signals transmitted by at least one of the elements, the phase shifter being a four bit or smaller phase shifter.
5 . The phased array as defined by claim 1 wherein each integrated circuit includes a splitter between a common arm and two side arms, each of the integrated circuits having a side arm beam gain control of no more than about 5 db.
6 . The phased array as defined by claim 1 wherein each integrated circuit is positioned between at least two elements.
7 . The phased array as defined by claim 1 wherein each integrated circuit is flip-chip bonded to the substrate, the integrated circuit having a bottom side forming an open space with the substrate.
8 . The phased array as defined by claim 1 further comprising a polarizer and a radome, the polarizer being between the substrate and the radome.
9 . The phased array as defined by claim 1 wherein each integrated circuit includes an active phase shifter.
10 . The phased array as defined by claim 1 wherein each integrated circuit is configured to use time division duplex waveforms to enable the phased array to be used for both transmission and receipt of signals.
11 . The phased array as defined by claim 1 wherein the plurality of integrated circuits are configured to operate the phased array using 5G protocols to transmit signals and/or receive signals.
12 . A communication apparatus comprising:
a printed circuit board having a front side;
a plurality of elements on the front side of the printed circuit forming a patch phased array;
a plurality of integrated circuits on the front side of the printed circuit board, the plurality of integrated circuits being wafer level chip scale packaging integrated circuits,
the plurality of integrated circuits having means for controlling receipt and/or transmission of signals by the plurality of elements in the patch phased array.
13 . The communication apparatus as defined by claim 12 wherein each integrated circuit is configured to control at least two elements.
14 . The communication apparatus as defined by claim 12 wherein each integrated circuit includes a phase shifter to control the phase of signals transmitted by at least one of the elements, the phase shifter being a four bit or smaller phase shifter.
15 . The communication apparatus as defined by claim 12 wherein each integrated includes a splitter between a common arm and two side arms, each of the integrated circuits having a side arm beam gain control of no more than about 5 db.
16 . The communication apparatus as defined by claim 12 further comprising a polarizer and a radome, the polarizer being between the printed circuit board and the radome.
17 . The communication apparatus as defined by claim 12 wherein each integrated is configured to use time division duplex waveforms to enable the phased array to be used for both transmission and receipt of signals.
18 . The communication apparatus as defined by claim 12 wherein the plurality of integrated circuits have means for operating the phased array at one or more frequencies of the Ka-band, Ku-band, and/or X-band to communicate with at least one satellite.
19 . The communication apparatus as defined by claim 12 wherein the plurality of integrated circuits are configured to operate the plurality of elements using 5G protocols to transmit signals and/or receive signals.
20 . The communication apparatus as defined by claim 12 wherein the plurality of elements forms a triangular lattice.
21 . A method of producing a phased array, the method comprising:
forming a plurality of elements on a front side of a laminar substrate to form a patch array;
flip chip mounting a plurality of integrated circuits to the front side of the laminar substrate, the plurality of integrated circuits being wafer level chip scale packaging integrated circuits, at least two of the plurality of elements having at least one integrated circuit therebetween,
the plurality of integrated circuits configured to control receipt and/or transmission of signals by the plurality of elements in the patch phased array,
the plurality of integrated circuits configured to operate the phased array at one or more frequencies of the Ka-band, Ku-band, and/or X-band to communicate with at least one satellite,
electrically connecting each of the plurality of integrated circuits to at least two elements.
22 . The method as defined by claim 21 further comprising securing a polarizer and a radome to the patch array, the polarizer being between the laminar substrate and the radome.
23 . The method as defined by claim 21 wherein each integrated circuit is configured to use time division duplex waveforms to enable the phased array to be used for both transmission and receipt of signals.
24 . The method as defined by claim 21 wherein forming comprises forming the plurality of elements in a triangular lattice on the substrate.
25 . The method as defined by claim 21 wherein each integrated circuit is configured to control at least two elements.
26 . The method as defined by claim 21 wherein each integrated circuit includes a phase shifter to control the phase of signals transmitted by at least one of the elements, the phase shifter being a four bit or smaller phase shifter.
27 . The method as defined by claim 21 wherein each integrated circuit includes a splitter between a common arm and two side arms, each of the integrated circuits having a side arm beam gain control of no more than about 5 db.