Nonvolatile memory with magnetoresistive element and transistor

1. A nonvolatile memory comprising:

first through fifth wirings; and

a memory cell including:

a first circuit including a first magnetoresistive element and a first select transistor, the first magnetoresistive element and the first select transistor being electrically connected in series, the first magnetoresistive element including a first reference layer, a first storage layer, and a first nonmagnetic layer between the first reference layer and the first storage layer;

a second circuit including a second magnetoresistive element and a second select transistor, the second magnetoresistive element and the second select transistor being electrically connected in series, the second magnetoresistive element including a second reference layer, a second storage layer, and a second nonmagnetic layer between the second reference layer and the second storage layer;

a third circuit including first and second transistors; and

a fourth circuit including third and fourth transistors, wherein

gates of the first and second select transistors are electrically connected to the first wiring,

one terminal of the first circuit and a gate of one of the third and fourth transistors of the fourth circuit are electrically connected to the second wiring,

one terminal of the second circuit and a gate of one of the first and second transistors of the third circuit are electrically connected to the third wiring,

the other terminal of the first circuit and a gate of the other one of the third and fourth transistors of the fourth circuit are electrically connected to the fourth wiring, and

the other terminal of the second circuit and a gate of the other one of the first and second transistors of the third circuit are electrically connected to the fifth wiring.

2. The memory according to claim 1 , wherein

the third circuit is a first path including the first transistor and the second transistor electrically connected in series, the first path including one terminal electrically connected to the first circuit and including the other terminal electrically connected to a first power supply terminal to be set to a first potential or a second power supply terminal to be set to a second potential lower than the first potential, and

the fourth circuit is a second path including the third transistor and the fourth transistor electrically connected in series, the second path including one terminal electrically connected to the second circuit and including the other terminal electrically connected to the first power supply terminal or the second power supply terminal.

3. The memory according to claim 2 , wherein

one terminal of the first magnetoresistive element is electrically connected to the second wiring, and

one terminal of the second magnetoresistive element is electrically connected to the third wiring.

4. The memory according to claim 2 , wherein

one terminal of the first select transistor is electrically connected to the second wiring, and

one terminal of the second select transistor is electrically connected to the third wiring.

5. The memory according to claim 1 , wherein the first through fourth transistors are p-channel transistors, or the first through fourth transistors are n-channel transistors.

6. The memory according to claim 1 , wherein the memory cell further includes:

a fifth circuit electrically connected in parallel to the first circuit, the fifth circuit including a third magnetoresistive element and a third select transistor, the third magnetoresistive element and the third select transistor being electrically connected in series, the third magnetoresistive element including a third reference layer, a third storage layer, and a third nonmagnetic layer between the third reference layer and the third storage layer; and

a sixth circuit electrically connected in parallel to the second circuit, the sixth circuit including a fourth magnetoresistive element and a fourth select transistor, the fourth magnetoresistive element and the fourth select transistor being electrically connected in series, the fourth magnetoresistive element including a fourth reference layer, a fourth storage layer, and a fourth nonmagnetic layer between the fourth reference layer and the fourth storage layer.

7. The memory according to claim 6 , wherein

one terminal of the first select transistor is electrically connected to the second wiring, and

one terminal of the second select transistor is electrically connected to the third wiring.

8. A nonvolatile memory comprising:

a plurality of first wirings;

a plurality of second wirings intersecting the first wirings;

a plurality of third wirings intersecting the first wirings;

a plurality of fourth wirings intersecting the first wirings;

a plurality of fifth wirings intersecting the first wirings;

a first circuit including first and second transistors;

a second circuit including third and fourth transistors; and

a plurality of memory cells, at least one of the memory cells including:

a third circuit including a first magnetoresistive element and a first select transistor, the first magnetoresistive element and the first select transistor being electrically connected in series, the first magnetoresistive element including a first reference layer, a first storage layer, and a first nonmagnetic layer between the first reference layer and the first storage layer; and

a fourth circuit including a second magnetoresistive element and a second select transistor, the second magnetoresistive element and the second select transistor being electrically connected in series, the second magnetoresistive element including a second reference layer, a second storage layer, and a second nonmagnetic layer between the second reference layer and the second storage layer, wherein

gates of the first and second select transistors are electrically connected to one of the first wirings,

one terminal of the third circuit and a gate of one of the third and fourth transistors of the second circuit are electrically connected to one of the second wirings,

one terminal of the fourth circuit and a gate of one of the first and second transistors of the first circuit are electrically connected to one of the third wirings,

the other terminal of the third circuit and a gate of the other one of the third and fourth transistors of the second circuit are electrically connected to one of the fourth wirings, and

the other terminal of the fourth circuit and a gate of the other one of the first and second transistors of the first circuit are electrically connected to one of the fifth wirings.

9. The memory according to claim 8 , wherein

the first circuit is a first path including the first transistor and the second transistor electrically connected in series, the first path including one terminal electrically connected to the third circuit and including the other terminal electrically connected to a first power supply terminal to be set to a first potential or a second power supply terminal to be set to a second potential lower than the first potential, and

the second circuit is a second path including the third transistor and the fourth transistor electrically connected in series, the second path including one terminal electrically connected to the fourth circuit and including the other terminal electrically connected to the first power supply terminal or the second power supply terminal.

10. The memory according to claim 8 , wherein

in each of two adjacent memory cells among the memory cells corresponding to one of the second wirings, a sequence of arrangement of the first magnetoresistive element and the first select transistor in a direction from the corresponding second wiring toward the corresponding fourth wiring in the third circuit is the same as a sequence of arrangement of the second magnetoresistive element and the second select transistor in a direction from the corresponding third wiring toward the corresponding fifth wiring in the fourth circuit, and

the sequence of arrangement of the first magnetoresistive element and the first select transistor in the direction from the corresponding second wiring toward the corresponding fourth wiring in the third circuit in one of the two memory cells differs from the sequence of arrangement of the first magnetoresistive element and the first select transistor in the direction from the corresponding second wiring toward the corresponding fourth wiring in the third circuit in the other one of the two memory cells.