Compiler global memory access optimization in code regions using most appropriate base pointer registers

1. A method comprising:

identifying, by a compiler executing on a processing system, a global memory access instruction within a set of code regions that include a set of global variable candidates to access a global memory; and

modifying, by the compiler executing on the processing system, the global memory access instruction, wherein the modified global memory access instruction utilizes an unused base pointer register of a set of unused base pointer register candidates within the set of code regions, a global variable from the set of global variable candidates to be used as a base address, and an offset relative to the base address to access the global memory.

2. The method of claim 1 , further comprising:

preventing, by the compiler, a linker from removing any global variable based on pre-linker information.

3. The method of claim 1 , further comprising:

preventing, by the compiler, a linker from aligning any global variable in the section that is optimized based on pre-linker information.

4. The method of claim 1 , wherein modifying the global memory access instruction considers the memory model in use from a set of architecture memory models.

5. The method of claim 4 , further comprising:

determining a set of associated costs of the modified global memory access instruction and a set of associated costs of the unmodified global memory access instruction.

6. The method of claim 5 , wherein the associated cost of the modified global memory access instruction is lower than the associated costs of the unmodified global memory access instruction.

7. The method of claim 5 , wherein the associated cost of the modified global memory access instruction includes:

a type of the unused base pointer register;

a speed to execute the modified global memory access instruction; and

a size of the modified global memory access instruction.

8. The method of claim 1 , wherein modifying the global memory access instruction is based on a set of constraints.

9. A processing device comprising:

a target processor instruction memory to store a plurality of target processor instructions that include a plurality of global memory access instructions; and

a compiler to communicate with the target processor instruction memory, the compiler including:

a global variable candidate detection module to identify a global memory access instruction within a set of code regions that use a set of global variable candidates to access a global memory; and

a memory access optimization module to modify the global memory access instruction, wherein the modified global memory access instruction utilizes an unused base pointer register of a set of unused base pointer register candidates within the set of code regions, a global variable from the set of global variable candidates to be used as a base address, and an offset relative to the base address to access the global memory.

10. The processing device of claim 9 , the compiler further to:

prevent a linker from removing any global variable.

11. The processing device of claim 9 , the compiler further to:

prevent a linker from aligning any global variable in the section that is optimized.

12. The processing device of claim 9 , wherein the modify the global memory access instruction considers the memory model in use from a set of architecture memory models.

13. The processing device of claim 12 , the memory access optimization module further to:

determine a set of associated costs of the modified global memory access instruction and a set of associated costs of the unmodified global memory access instruction.

14. The processing device of claim 13 , wherein the set of associated costs of the modified global memory access instruction is lower than the associated costs of the unmodified global memory access instruction.

15. The processing device of claim 13 , wherein the associated cost of the modified global memory access instruction includes:

a type of the unused base pointer register;

a speed to execute the modified global memory access instruction; and

a size of the modified global memory access instruction.

16. The processing device of claim 9 , wherein modifying the global memory access instruction is based on a set of constraints.

17. A method comprising:

identifying, by a compiler executing on a processing system, a global memory access instruction within a set of code regions that include a set of global variable candidates to access a global memory; and

modifying, by the compiler executing on the processing system, the global memory access instruction, wherein the modified global memory access instruction utilizes an unused base pointer register of a set of unused base pointer register candidates within the set of code regions, a global variable from the set of global variable candidates to be used as base address, and an offset relative to the base address to access the global memory, wherein modifying the global memory access instruction is based on a set of associated costs of the modified global memory access instruction and a set of associated costs of the unmodified global memory access instruction.

18. The method of claim 17 , further comprising:

preventing, by the compiler, a linker from removing any global variable.

19. The method of claim 17 , further comprising:

preventing, by the compiler, a linker from aligning any global variable in the section that is optimized.

20. The method of claim 17 , wherein modifying the global memory access instruction considers the memory model in use from a set of architecture memory models.