System and method for adjusting boot interface frequency

1. A system-on-chip (SOC) configured to boot from an external memory storing a boot program and a predefined data pattern, the SOC comprising:

a processing core configured to boot according to the boot program stored in the external memory;

a memory controller connected between the processing core and the external memory, wherein the memory controller is connected to the external memory via an interface bus;

a clock manager that receives an external clock signal and generates an internal clock signal, wherein the clock manager includes a plurality of phase-lock-loop (PLL) circuits;

a clock divider that receives the internal clock signal and outputs a divided clock signal, wherein the memory controller uses the divided clock signal to establish an interface frequency for communication with the external memory;

a Boot Read-Only-Memory (ROM), connected to the processing core, for storing a set of initial boot instructions executed by the processing core before executing the boot program stored in the external memory; and

a boot control logic circuit, connected to the clock divider, that compares a check data pattern to the predefined data pattern, wherein the predefined data pattern is read from the external memory by the memory controller at the interface frequency established by the divided clock signal, and wherein:

(i) when the predefined and check data patterns do not match, the boot control logic circuit causes the clock divider to adjust the divided clock signal to change the interface frequency, after which reading of the predefined data pattern and comparison to the check data pattern are repeated, and

(ii) when the predefined and check data patterns match, the memory controller reads the boot program from the external memory at the interface frequency defined by the divided clock signal and reads reset configuration words from the external memory, the clock manager uses the reset configuration words to configure the PLL circuits, and the Boot ROM reprograms the clock divider according to the PLL circuit configurations such that the memory controller reads the boot program using the interface frequency at which the check and predefined data patterns were determined to match.

2. The SOC of claim 1 , wherein the memory controller is an integrated flash controller.

3. The SOC of claim 2 , wherein at least one of the clock divider and the boot control logic circuit is part of the integrated flash controller.

4. The SOC of claim 1 , wherein the boot control logic circuit is part of the Boot ROM.

5. The SOC of claim 1 , wherein changing the interface frequency involves lowering the interface frequency.

6. The SOC of claim 5 , wherein the boot control logic circuit determines whether a frequency of the divided clock signal is lower than a predetermined minimum frequency, and outputs an error signal when the divided clock signal frequency is lower than the predetermined minimum frequency.

7. The SOC of claim 1 , wherein the memory controller is a flash memory controller.

8. A method of booting a system-on-chip (SOC) according to a boot program stored in an external memory, the SOC including a processing core, a memory controller connected with the external memory via an interface bus, a clock divider, a boot control logic circuit, a Boot Read-Only-Memory (ROM), connected to the processing core, for storing a set of initial boot instructions, and a clock manager that generates an input clock signal, wherein the clock manager includes a plurality of phase-lock-loop (PLL) circuits, the method comprising:

(a) powering on the processing core and executing, by the processing core, the initial boot instructions;

(b) reading, by the memory controller, a predefined data pattern from the external memory according to an interface frequency, the interface frequency being based on a clock signal output by the clock divider;

(c) comparing, by the boot control logic circuit, a check data pattern to the read predefined data pattern;

(d) when the check and predefined data patterns do not match, instructing the clock divider to adjust the clock signal to change the interface frequency, and repeating steps (b)-(c);

(e) when the check and predefined data patterns match, reading, by the memory controller, the boot program from the external memory according to the interface frequency, and requesting, by the Boot ROM, the memory controller to read reset configuration words from the external memory;

(f) configuring the PLL circuits in the clock manager using the read reset configuration words; and

(g) reprogramming, by the Boot ROM, the clock divider according to the PLL circuit configurations such that the memory controller reads the boot program using the interface frequency at which the check and predefined data patterns were determined to match.

9. The method of claim 8 , further comprising sending, by the Boot ROM, instructions to the memory controller to read the predefined data pattern from the external memory.

10. The method of claim 8 , wherein the boot control logic circuit is part of the Boot ROM.

11. The method of claim 8 , wherein adjusting the clock signal output by the clock divider involves lowering a frequency of the clock signal.

12. The method of claim 11 , further comprising outputting an error when the frequency of the clock signal output by the clock divider falls below a predetermined threshold level.