Vertical FET with strained channel
A transistor in an integrated circuit device is formed using fabrication processes that include techniques to create a strain in the channel material, thereby improving the performance of the transistor. In one or more embodiments, an initial transistor structure is formed including a substrate, a dummy fin, and a hard mask. The dummy fin structure is narrowed. A channel is epitaxially grown on the dummy fin structure to create a strain on the channel. A first gate stack is formed over the channel. The hard mask and dummy fin are removed. A second gate stack is formed over the channel. Excess material is removed from the second gate stack. The formation of the transistor is finalized using a variety of techniques.
1. A method of forming a transistor in an integrated circuit device, the method comprising:
forming an initial transistor structure including a substrate, a dummy fin, and a hard mask;
reducing a width dimension of the dummy fin structure;
epitaxially growing a channel on the dummy fin structure to create a strain on the channel;
forming a first gate stack adjacent to the channel;
removing the hard mask and dummy fin;
forming a second gate stack over the channel; and
removing excess material from the second gate stack.
2. The method of claim 1 wherein:
the dummy fin comprises silicon; and
the epitaxially grown channel comprises silicon germanium; wherein:
a lattice mismatch between silicon and silicon germanium causes the silicon germanium channel to have a compressive strain.
3. The method of claim 1 wherein:
the dummy fin comprises silicon germanium; and
the epitaxially grown channel comprises silicon; wherein:
a lattice mismatch between silicon and silicon germanium causes the silicon channel to have a tensile strain.
4. The method of claim 1 wherein:
the hard mask comprises an oxide and a nitride.
5. The method of claim 1 wherein:
the first gate stack comprises a first high-k material which is below a first work function metal, which is below a first gate material.
6. The method of claim 5 wherein:
the second gate stack comprises a second high-k material which is below a second work function metal, which is below a second gate material.
7. The method of claim 5 wherein:
the first gate stack further comprises a bottom spacer below the first high-k material.
8. The method of claim 5 wherein the first gate material is selected from a polysilicon or a tungsten-based material.
9. The method of claim 1 wherein:
removing the hard mask and dummy fin comprises using a selective etch technique to remove the hard mask and dummy fin without affecting the channel.
10. The method of claim 1 further comprising:
placing a bottom spacer over the substrate prior to epitaxially growing the channel on the dummy fin structure.