VSS LDPC decoder with improved throughput for hard decoding

1. A memory system, comprising:

a memory device; and

a processor in communication with, and configured to control, the memory device, wherein the memory device includes:

a memory storage; and

a read processor coupled with the memory storage, wherein the read processor includes a pre-processing checksum unit and a low-density parity-check (LDPC) decoder that share registers and memory,

the pre-processing checksum unit configured to, during a first decoding iteration:

receive hard read data including channel input (Lch) sign values, wherein the hard read data corresponds to data read from the memory storage;

compute a checksum of the Lch sign values and conduct a parity check, as a checksum_pre value; and

output the checksum_pre value to the LDPC decoder;

the LDPC decoder including an Lch memory and a checksum update unit, the LDPC decoder configured to,

during the first decoding iteration:

store the checksum_pre value received from the pre-processing checksum unit in the Lch memory of the LDPC decoder;

receive, by the checksum update unit, the checksum_pre value; and

pipeline the checksum_pre value for a second decoding iteration, wherein the LDPC decoder does not perform error correction during the first decoding iteration; and

in at least the second decoding iteration,

decode a codeword, using the registers and memory shared with the pre-processing checksum unit, based at least in part on the computed and received checksum_pre value, which includes the parity check on the hard read data operations performed by the pre-processing checksum unit in the first decoding iteration; and

update the checksum value, using the checksum update unit, for a next decoding iteration when the second decoding iteration fails; and

return the decoded codeword when the second decoding iteration is successful.

2. The memory system of claim 1 , wherein the LDPC decoder further includes a check node update (CNU) unit configured to store the Lch sign values stored in the Lch memory as a sgn_mem value during the second decoding iteration.

3. The memory system of claim 1 , wherein the LDPC decoder further includes a check node update (CNU) unit configured to receive the checksum_pre value during the first decoding iteration and store the checksum_pre value as an all_sgn value.

4. The memory system of claim 1 , wherein the LDPC decoder comprises a min-sum LDPC decoder.

5. The memory system of claim 1 , wherein the LDPC decoder further includes a check node update (CNU) unit configured to initialize a minimum read value field and a minimum read value location field at the beginning of the second decoding iteration.

6. The memory system of claim 1 , wherein the LDPC decoder is available for decoding from the second decoding iteration to the final decoding iteration.

7. A method, comprising:

receiving, with a pre-processing checksum unit of a read processor of a memory device, hard read data including channel input Lch sign values, wherein the hard read data corresponds to data read from a memory storage of the memory device;

computing, using the pre-processing checksum unit, a checksum of the Lch sign values and conducting a parity check, as a checksum_pre value;

outputting the checksum_pre value to a low-density parity-check (LDPC) decoder of the read processor;

during a first decoding iteration:

storing, by the LDPC decoder, the checksum_pre value received from the pre-processing checksum unit in a Lch memory of the LDPC decoder;

receiving, by a checksum update unit of the LDPC decoder, the checksum_pre value; and

pipelining, by the LDPC decoder, the checksum_pre value for a second decoding iteration, wherein the LDPC decoder does not perform error correction during the first decoding iteration; and

in at least the second decoding iteration,

decoding, using the LDPC decoder and registers and memory shared by the LDPC decoder and the pre-processing checksum unit, a codeword based at least in part on the computed and received checksum_pre value, which includes the parity check on the hard read operations performed by the pre-processing checksum unit in the first decoding iteration; and

update the checksum value, using the checksum update unit, for a next decoding iteration when the second decoding iteration fails; and

returning the decoded codeword when the second decoding iteration is successful.

8. The method of claim 7 , further comprising storing, with a check node update unit of the LDPC decoder, the Lch sign values stored in the Lch memory as a sgn_mem value during the second decoding iteration.

9. The method of claim 7 , further comprising receiving, with a check node update unit of the LDPC decoder, the checksum_pre value during the first decoding iteration and storing the checksum_pre value as an all_sgn value.

10. The method of claim 7 , wherein the LDPC decoder comprises a min-sum LDPC decoder.

11. The method of claim 7 , further comprising initializing, with a check node update unit of the LDPC decoder, a minimum read value field and a minimum read value location field at the beginning of the second decoding iteration.

12. The method of claim 7 , wherein the LDPC decoder is available for decoding from the second decoding iteration to the final decoding iteration.

13. A memory device, comprising:

a memory storage; and

a read processor coupled with the memory storage, wherein the read processor includes a pre-processing checksum unit and a low-density parity-check (LDPC) decoder that share registers and memory, the pre-processing checksum unit configured to, during a first decoding iteration:

receive hard read data including channel input (Lch) sign values, wherein the hard read data corresponds to data read from the memory storage;

compute a checksum of the Lch sign values and conduct a parity check, as a checksum_pre value; and

output the checksum_pre value to the LDPC decoder;

the LDPC decoder including an Lch memory and a checksum update unit, the LDPC decoder configured to,

during the first decoding iteration:

store the checksum_pre value received from the pre-processing checksum unit in the Lch memory of the LDPC decoder;

receive, by the checksum update unit, the checksum_pre value;

pipeline the checksum_pre value for a second decoding iteration, wherein the LDPC decoder does not perform error correction during the first decoding iteration; and

in at least the second decoding iteration,

decode a codeword, using the registers and memory shared with the pre-processing checksum unit, based at least in part on the computed and received checksum_pre value, which includes the parity check on the hard read data operations performed by the pre-processing checksum unit in the first decoding iteration; and

update the checksum value, using the checksum update unit, for a next decoding iteration when the second decoding iteration fails; and

return the decoded codeword when the second decoding iteration is successful.

14. The memory device of claim 13 , wherein the LDPC decoder further includes a check node update (CNU) unit configured to store the Lch sign values stored in the Lch memory as a sgn_mem value during the second decoding iteration.

15. The memory device of claim 13 , wherein the LDPC decoder further includes a check node update (CNU) unit configured to receive the checksum_pre value during the first decoding iteration and store the checksum_pre value as an all_sgn value.

16. The memory device of claim 13 , wherein the LDPC decoder comprises a min-sum LDPC decoder.

17. The memory device of claim 13 , wherein the LDPC decoder further includes a check node update (CNU) unit configured to initialize a minimum read value field and a minimum read value location field at the beginning of the second decoding iteration.

18. The memory device of claim 13 , wherein the LDPC decoder is available for decoding from the second decoding iteration to the final decoding iteration.