Apparatus and methods for fractional-N phase-locked loops with multi-phase oscillators
Apparatus and methods for fractional-N synthesizer phase-locked loops with multi-phase oscillators are provided. In certain configurations, a fractional-N PLL includes a time-to-digital converter (TDC), a digital loop filter, a multi-phase oscillator, and fractional division circuitry. The multi-phase oscillator includes multiple taps used to generate multiple clock signal phases that are provided to the fractional division circuitry to reduce the fractional-N PLL's quantization error. The fractional division circuitry includes a tap error correction circuit for compensating for errors in tap positions of the multi-phase oscillator. By including the tap error correction circuit, the phase noise and/or jitter performance of the fractional-N PLL can be enhanced.
1. A phase-locked loop (PLL) having low jitter, the PLL comprising:
a time-to-digital converter (TDC) configured to generate a TDC output signal based on a reference clock signal and a feedback clock signal;
a digital loop filter configured to process the TDC output signal to generate a digital frequency control signal;
a multi-phase oscillator comprising a plurality of taps configured to provide a plurality of clock signal phases, wherein a frequency of the multi-phase oscillator is controllable by the digital frequency control signal; and
fractional division circuitry configured to receive the plurality of clock signal phases and to generate the feedback clock signal, wherein the fractional division circuitry comprises a tap error correction circuit configured to compensate for a plurality of tap errors of the plurality of taps of the multi-phase oscillator.
2. The PLL of claim 1 , wherein the tap error correction circuit is configured to detect the tap errors based on processing the TDC output signal.
3. The PLL of claim 2 , wherein the tap error correction circuit is further configured to calculate a running average for at least a portion of the tap errors.
4. The PLL of claim 1 , wherein the fractional division circuitry comprises a fractional divider and a modulator configured to control a division operation of the fractional divider.
5. The PLL of claim 4 , wherein the tap error correction circuit is configured to compensate for the tap errors based on adjusting a value of an input signal to the modulator.
6. The PLL of claim 4 , wherein the tap error correction circuit comprises a tap error measurement circuit configured to receive the TDC output signal and to generate a tap error correction signal.
7. The PLL of claim 6 , wherein the tap error correction circuit is configured to generate an error signal based on a difference between the tap error correction signal and an output signal of the modulator.
8. The PLL of claim 7 , wherein the tap error correction circuit is configured to adjust a value of an input signal to the modulator based on the error signal.
9. The PLL of claim 1 , wherein the multi-phase oscillator comprises a rotary traveling wave oscillator (RTWO).
10. The PLL of claim 1 , wherein the plurality of taps comprises at least 10 taps.
11. A method of fractional frequency synthesis, the method comprising:
generating a time-to-digital converter (TDC) output signal by performing time-to-digital conversion based on a reference clock signal and a feedback clock signal;
digitally filtering the TDC output signal to generate a digital frequency control signal;
controlling a frequency of a multi-phase oscillator using the digital frequency control signal;
generating a plurality of clock signal phases using a plurality of taps of the multi-phase oscillator;
generating the feedback clock signal based on the plurality of clock signal phases; and
compensating for a plurality of tap errors of the plurality of taps of the multi-phase oscillator.
12. The method of claim 11 , wherein compensating for the tap errors comprises detecting the tap errors based on processing the TDC output signal.
13. The method of claim 11 , further comprising calculating a running average of at least a portion of the tap errors.
14. The method of claim 11 , wherein compensating for the tap errors comprises adjusting a value of an input signal to a modulator.
15. The method of claim 14 , further comprising generating a tap error correction signal based on processing the TDC output signal to detect the tap errors.
16. The method of claim 14 , further comprising generating an error signal based on a difference between the tap error correction signal and an output signal of the modulator.
17. The method of claim 16 , further comprising adjusting the value of the input signal to the modulator based on the error signal.
18. The method of claim 11 , further comprising generating the plurality of clock signal phases using a rotary traveling wave oscillator (RTWO).
19. A phase-locked loop (PLL) having low jitter, the PLL comprising:
a time-to-digital converter (TDC) configured to generate a TDC output signal based on a reference clock signal and a feedback clock signal;
a digital loop filter configured to process the TDC output signal to generate a digital frequency control signal;
a multi-phase oscillator comprising a plurality of taps configured to provide a plurality of clock signal phases, wherein a frequency of the multi-phase oscillator is controllable by the digital frequency control signal; and
fractional division circuitry configured to receive the plurality of clock signal phases and to generate the feedback clock signal, wherein the fractional division circuitry comprises means for compensating for a plurality of tap errors of the plurality of taps of the multi-phase oscillator.
20. The PLL of claim 19 , wherein the multi-phase oscillator comprises a rotary traveling wave oscillator (RTWO).