Semiconductor memory device
A semiconductor memory device according to an embodiment comprises: a plurality of control gate electrodes arranged in a first direction intersecting an upper surface of a substrate; a semiconductor layer extending in the first direction and facing a plurality of the control gate electrodes from a second direction intersecting the first direction; and a gate insulating layer provided between the control gate electrode and the semiconductor layer. The semiconductor layer comprises: a first portion extending in the first direction and facing a plurality of the control gate electrodes; and a second portion provided on a closer side to the substrate than this first portion. A film thickness of the first portion in the second direction is larger than a film thickness of the second portion in the second direction. A crystal grain included in the first portion is larger than a crystal grain included in the second portion.
1. A semiconductor memory device, comprising:
a plurality of control gate electrodes arranged in a first direction intersecting an upper surface of a substrate;
a first semiconductor layer extending in the first direction and facing a plurality of the control gate electrodes from a second direction intersecting the first direction; and
a gate insulating layer provided between the control gate electrode and the first semiconductor layer,
the first semiconductor layer comprising:
a first portion extending in the first direction and facing the control gate electrode; and
a second portion provided on a closer side to the substrate than the first portion,
a film thickness of the first portion in the second direction being larger than a film thickness of the second portion in the second direction, and
a crystal grain included in the first portion being larger than a crystal grain included in the second portion.
2. The semiconductor memory device according to claim 1 , wherein
the first portion includes a crystal grain larger than a film thickness of the first portion in the second direction.
3. The semiconductor memory device according to claim 1 , wherein
the crystal grain included in the first portion is larger than a film thickness of the first portion in the second portion, and
the crystal grain included in the second portion is smaller than a film thickness of the second portion in the second portion.
4. The semiconductor memory device according to claim 1 , further comprising
a second semiconductor layer connected to an end of the first semiconductor layer on a side of the substrate.
5. The semiconductor memory device according to claim 1 , wherein
the first semiconductor layer further comprises a third portion provided between the first portion and the second portion, and
the third portion includes a metal atom.
6. The semiconductor memory device according to claim 5 , wherein
the third portion includes a silicide.
7. The semiconductor memory device according to claim 1 , wherein
the gate insulating layer includes a charge accumulation part.
8. A semiconductor memory device, comprising:
a plurality of control gate electrodes arranged in a first direction intersecting an upper surface of a substrate;
a first semiconductor layer extending in the first direction and facing a plurality of the control gate electrodes from a second direction intersecting the first direction; and
a gate insulating layer provided between the control gate electrode and the first semiconductor layer,
the first semiconductor layer comprising:
a first portion extending in the first direction and facing the control gate electrode; and
a second portion provided on a closer side to the substrate than the first portion,
a film thickness of the first portion in the second direction being larger than a film thickness of the second portion in the second direction,
the first portion including a crystal grain larger than the film thickness of the first portion in the second direction, and
the second portion including a monocrystal.
9. The semiconductor memory device according to claim 8 , further comprising
a second semiconductor layer connected to an end of the first semiconductor layer on a side of the substrate.
10. The semiconductor memory device according to claim 9 ,
wherein the second semiconductor layer includes a monocrystal, and
the monocrystal included in the second portion of the first semiconductor layer has an orientation plane aligned with that of the monocrystal included in the second semiconductor layer.
11. The semiconductor memory device according to claim 8 , wherein
the first semiconductor layer further comprises a third portion provided between the first portion and the second portion, and
the third portion includes a metal atom.
12. The semiconductor memory device according to claim 11 , wherein
the third portion includes a silicide.
13. The semiconductor memory device according to claim 8 , wherein
the gate insulating layer includes a charge accumulation part.
14. A semiconductor memory device, comprising:
a plurality of control gate electrodes arranged in a first direction intersecting an upper surface of a substrate;
a semiconductor layer extending in the first direction and facing a plurality of the control gate electrodes from a second direction intersecting the first direction; and
a gate insulating layer provided between the control gate electrode and the semiconductor layer,
the semiconductor layer comprising:
a first portion extending in the first direction and facing the control gate electrode;
a second portion provided on a closer side to the substrate than the first portion; and
a third portion provided between the first portion and the second portion,
a film thickness of the first portion in the second direction being larger than a film thickness of the second portion in the second direction, and
the third portion including a metal atom of nickel (Ni), cobalt (Co), aluminum (Al), or palladium (Pd).
15. The semiconductor memory device according to claim 14 , wherein
the third portion includes a silicide.
16. The semiconductor memory device according to claim 14 , wherein
the gate insulating layer includes a charge accumulation part.