Semiconductor memory device

1. A semiconductor memory device, including a memory cell array, the memory cell array including a plurality of memory cells, the memory cell array comprising:

a plurality of first conductive layers that are stacked in a first direction above a substrate and extend in a second direction intersecting the first direction;

a plurality of second conductive layers that are stacked in the first direction above the substrate and extend in the second direction, the plurality of second conductive layers being adjacent to the plurality of the first conductive layers in a third direction intersecting the first direction and the second direction;

a third conductive layer extending in the first direction;

a first variable resistance film provided at intersections of the plurality of first conductive layers and the third conductive layer;

a second variable resistance film provided at intersections of the plurality of second conductive layers and the third conductive layer;

a first select transistor disposed closer to the substrate than a lowermost layer of the plurality of first conductive layers, the first select transistor including a first select gate line intersecting the third conductive layer;

a fourth conductive layer that extends in the third direction and is connected to a lower end of the third conductive layer via the first select transistor; and

a second select transistor disposed between at least one pair of the plurality of first conductive layers adjacent in the first direction, the second select transistor including a second select gate line intersecting the third conductive layer.

2. The semiconductor memory device according to claim 1 , wherein two layers of the first select gate lines are provided continuously via an inter-layer insulating film along the first direction.

3. The semiconductor memory device according to claim 1 , wherein the second select gate line has an average width substantially identical to that of the first conductive layer in a direction orthogonal to the first direction and the second direction.

4. The semiconductor memory device according to claim 1 , wherein in the first direction, an average of thickness of the second select gate line is larger than an average of thickness of the first conductive layer.

5. The semiconductor memory device according to claim 1 , further comprising:

a fifth conductive layer extending in the third direction and electrically connected to an upper end of the third conductive layer; and

a third select transistor disposed between the fifth conductive layer and an uppermost layer of the plurality of first conductive layers, the third select transistor including a third select gate line intersecting the third conductive layer.

6. The semiconductor memory device according to claim 1 , wherein one of the first conductive layers is configured from a plurality of regions that are electrically independent.

7. The semiconductor memory device according to claim 1 , wherein the second select gate line disposed between the plurality of first conductive layers adjacent in the first direction has a shape substantially identical to that of one of the first conductive layers when viewed in the first direction.

8. The semiconductor memory device according to claim 1 , wherein the first variable resistance film is divided between intersections of the plurality of first conductive layers and the third conductive layer, and an insulating layer is disposed between the first variable resistance films divided in the first direction.

9. The semiconductor memory device according to claim 1 , wherein the first variable resistance film is disposed between the first select gate line and the third conductive layer.

10. The semiconductor memory device according to claim 1 , wherein an insulating film including silicon is disposed between the first select gate line and the third conductive layer.

11. The semiconductor memory device according to claim 1 , further comprising:

a plurality of sixth conductive layers that are stacked in the first direction above the substrate and extend in the second direction, the plurality of sixth conductive layers being adjacent to the plurality of second conductive layers in the third direction;

a seventh conductive layer that is provided between the plurality of sixth conductive layers and the plurality of second conductive layers and extends in the first direction;

a third variable resistance film provided at intersections of the plurality of second conductive layers and the seventh conductive layer; and

a fourth variable resistance film provided at intersections of the plurality of sixth conductive layers and the seventh conductive layer.

12. The semiconductor memory device according to claim 11 , wherein the plurality of the first conductive layers and the plurality of sixth layers are electrically connected via an electrode member that is made of an identical material to the plurality of first conductive layers and the plurality of sixth layers and is extending in the third direction.

13. The semiconductor memory device according to claim 1 , further comprising:

an eighth conductive layer that is provided adjacent to the third conductive layer in the second direction and between the plurality of first conductive layers and the plurality of second layers, the eighth conductive layer being extending in the first direction; and

an insulating layer provided between the third conductive layer and the eighth conductive layer.