HBM with in-memory cache manager
A system and method for using high bandwidth memory as cache memory. A high bandwidth memory may include a logic die, and, stacked on the logic die, a plurality of dynamic read-only memory dies. The logic die may include a cache manager, that may interface to external systems through an external interface conforming to the JESD235A standard, and that may include an address translator, a command translator, and a tag comparator. The address translator may translate each physical address received through the external interface into a tag value, a tag address in the stack of memory dies, and a data address in the stack of memory dies. The tag comparator may determine whether a cache hit or cache miss has occurred, according to whether the tag value generated by the address translator matches the tag value stored at the tag address.
1. A memory system, comprising:
a memory stack comprising a plurality of memory dies; and
a logic die,
the memory dies being stacked on, and connected to, the logic die,
the logic die having an external interface to a host processor,
the logic die comprising a cache manager configured to:
translate an address received, as part of a command, through the external interface, to produce:
a first tag value, and
a tag address,
fetch a second tag value from a location in the memory stack corresponding to the tag address,
compare the first tag value and the second tag value, and
execute the command, based on the comparing of the first tag value and the second tag value.
2. The memory system of claim 1 , wherein the cache manager comprises an address translator configured to translate the address received through the external interface to produce:
the first tag value;
a data address in the memory stack; and
the tag address in the memory stack.
3. The memory system of claim 2 , wherein the cache manager comprises a command translator configured to generate, in response to a read command received through the external interface:
a first command to fetch the second tag value; and
a second command to fetch a data word.
4. The memory system of claim 3 , wherein the cache manager comprises a tag comparator to generate a cache hit signal, the cache hit signal having;
a value of true when the first tag value equals the second tag value; and
a value of false when the first tag value does not equal the second tag value.
5. The memory system of claim 4 , wherein the tag comparator is configured to send the cache hit signal through a first pin of the external interface.
6. The memory system of claim 5 , wherein the cache manager is configured to send the value of a dirty bit and/or the value of a valid bit through a second pin of the external interface.
7. The memory system of claim 5 , wherein the cache manager is configured to send the cache hit signal through the first pin, during a first interval of time, and to send the value of a dirty bit thorough the first pin, during a second interval.
8. The memory system of claim 3 , wherein the cache manager is configured to execute the first command through a pseudo channel.
9. The memory system of claim 3 , wherein the cache manager comprises a mode selector to indicate either that a parallel mode of operation is selected or that a serial mode of operation is selected, the cache manager being configured:
to execute the first command in parallel with the second command when the mode selector indicates that a parallel mode of operation is selected; and
to execute the first command before executing the second command when the mode selector indicates that the serial mode of operation is selected.
10. The memory system of claim 9 , wherein the mode selector is configured to be controlled through the external interface.
11. The memory system of claim 1 , wherein for any two data words stored in a first bank in the memory dies and accessible through different pseudo channels, two corresponding tags are stored in different subarrays of the memory stack.
12. The memory system of claim 1 , wherein the external interface is configured to operate in compliance with Joint Electron Device Engineering Council standard JESD235A.
13. A processing system, comprising:
a host processor;
a first memory system connected to the host processor; and
a second memory system connected to the host processor,
the first memory system comprising:
a memory stack comprising a plurality of memory dies; and
a logic die,
the memory dies being stacked on, and connected to, the logic die,
the logic die having an external interface to the host processor,
the logic die comprising a cache manager configured to:
translate an address received, as part of a command, through the external interface to produce:
a first tag value, and
a tag address,
fetch a second tag value from a location in the memory stack corresponding to the tag address,
compare the first tag value and the second tag value, and
execute the command, based on the comparing of the first tag value and the second tag value,
the second memory system being configured as backing store for the first memory system.
14. The processing system of claim 13 , wherein the cache manager comprises an address translator configured to translate the address received from the host processor through the external interface to produce:
the first tag value;
a data address in the memory stack; and
the tag address in the memory stack.
15. The processing system of claim 14 , wherein the cache manager comprises a command translator configured to generate, in response to a read command received from the host processor through the external interface:
a first command to fetch the second tag value; and
a second command to fetch a data word.
16. The processing system of claim 15 , wherein the cache manager comprises a tag comparator to generate a cache hit signal, the cache hit signal having;
a value of true when the first tag value equals the second tag value; and
a value of false when the first tag value does not equal the second tag value.
17. The processing system of claim 13 , wherein the external interface is configured to operate in compliance with Joint Electron Device Engineering Council standard JESD235A.
18. A method for operating a memory stack comprising a plurality of memory dies and a logic die, the memory dies being stacked on, and connected to, the logic die, the logic die having an external interface to a host processor, the method comprising:
translating, by the logic die, an address received, as part of a command, through the external interface to produce:
a first tag value;
a data address in the memory stack; and
a tag address in the memory stack;
fetching a second tag value from a location in the memory stack corresponding to the tag address;
comparing the first tag value and the second tag value; and
executing the command, based on the comparing of the first tag value and the second tag value.
19. The method of claim 18 , further comprising, generating, by the logic die, in response to a read command received through the external interface:
a first command to fetch the second tag value; and
a second command to fetch a data word.
20. The method of claim 19 , further comprising, generating, by the logic die, a cache hit signal, the cache hit signal having;
a value of true when the first tag value equals the second tag value; and
a value of false when the first tag value does not equal the second tag value.