Hybrid high bandwidth memories
A high bandwidth memory is provided. The high bandwidth memory includes a region of dynamic random access memory devices, a region of non-volatile memory devices adjacent to the region of dynamic random access memory devices, and a region of logic devices adjacent to both the region of dynamic random access memory devices and the region of non-volatile memory devices.
1 . A high bandwidth memory, comprising:
a region of dynamic random access memory devices;
a region of non-volatile memory devices laterally adjacent to the region of dynamic random access memory devices and above a substrate;
a region of logic devices laterally adjacent to both the region of dynamic random access memory devices and the region of non-volatile memory devices;
a dielectric fill between the logic devices, between the non-volatile memory devices, and between the dynamic random access memory devices, having a top surface at a first level;
an interlayer dielectric on the dielectric fill in the region of logic devices and the region of non-volatile memory devices, having a top surface at a second level and having a trench between the region of non-volatile memory devices and the region of logic devices; and
a protective spacer layer, extending over the interlayer dielectric in the region of non-volatile memory devices, the region of logic devices, and the region of dynamic random access memory devices, and being in direct contact with a vertical sidewall of the trench, electrically insulating the region of non-volatile memory devices and the region of logic devices from the region of dynamic random access memory devices, the protective spacer layer having a top surface in the region of dynamic random access memory devices that is consistently lower than the second level.
2 . The high bandwidth memory of claim 1 , further comprising a protective spacer layer separating the region of logic devices from the region of non-volatile memory devices.
3 . The high bandwidth memory of claim 1 , wherein the region of non-volatile memory devices includes a memory material layer between a top memory electrode and a bottom memory electrode.
4 . The high bandwidth memory of claim 1 , wherein the protective spacer layer is a dielectric material selected from the group consisting of silicon oxycarbide (SiOC), silicon carbide (SiC), silicon nitride (SiN), aluminum nitride (AlNx), and aluminum oxide (AlOx).
5 . The high bandwidth memory of claim 1 , further comprising a bottom capacitor electrode layer on a Storage Node Contact in the region of dynamic random access memory devices.
6 . The high bandwidth memory of claim 5 , further comprising a capacitor dielectric layer on the bottom capacitor electrode layer, and a top capacitor electrode layer on the capacitor dielectric layer in the region of dynamic random access memory devices.
7 . The high bandwidth memory of claim 6 , further comprising a supporting mesh, wherein the bottom capacitor electrode layer is in contact with the supporting mesh.
8 . The high bandwidth memory of claim 7 , wherein the supporting mesh is selected from the group of a dielectric oxide materials consisting of silicon oxide (SiO), silicon oxycarbide (SiOC), and aluminum oxide (AlOx).
9 . A high bandwidth memory, comprising:
a region of dynamic random access memory devices;
a region of non-volatile memory devices laterally adjacent to the region of dynamic random access memory devices;
a region of logic devices laterally adjacent to both the region of dynamic random access memory devices and the region of non-volatile memory devices;
a dielectric fill between the logic devices, between the non-volatile memory devices, and between the dynamic random access memory devices, having a top surface at a first level;
an interlayer dielectric on the dielectric fill in the region of logic devices and the region of non-volatile memory devices, having a top surface at a second level and having a trench between the region of non-volatile memory devices and the region of logic devices; and
a protective spacer layer, extending over the region of non-volatile memory devices, the region of logic devices, and the region of dynamic random access memory devices, and being in direct contact with a vertical sidewall of the trench, that electrically insulates the region of non-volatile memory devices and the region of logic devices from the region of dynamic random access memory devices and the region of logic devices from the region of dynamic random access memory devices, the protective spacer layer having a top surface in the region of dynamic random access memory devices that is consistently lower than the second level.
10 . The high bandwidth memory of claim 9 , wherein the protective spacer layer is a dielectric material selected from the group consisting of silicon oxycarbide (SiOC), silicon carbide (SiC), silicon nitride (SiN), aluminum nitride (AlNx), and aluminum oxide (AlOx).
11 . The high bandwidth memory of claim 9 , wherein the region of non-volatile memory devices includes a memory material layer between a top memory electrode and a bottom memory electrode.
12 . The high bandwidth memory of claim 11 , further comprising a cover layer in the region of logic devices and the region of non-volatile memory devices, wherein the cover layer is on the memory material layer between the top memory electrode and the bottom memory electrode.
13 . The high bandwidth memory of claim 9 , further comprising a bottom capacitor electrode layer on a Storage Node Contact in the region of dynamic random access memory devices.
14 . The high bandwidth memory of claim 13 , further comprising a capacitor dielectric layer on the bottom capacitor electrode layer, and a top capacitor electrode layer on the capacitor dielectric layer in the region of dynamic random access memory devices.